| Boom: a heuristic boolean minimizer J Hlavicka, P Fišer Proceedings of the 2001 IEEE/ACM international conference on Computer-aided …, 2001 | 90 | 2001 |
| Boom-a heuristic boolean minimizer P Fišer, J Hlavička Computing and informatics 22 (1), 19-51, 2003 | 63 | 2003 |
| Fault tolerant system design method based on self-checking circuits P Kubalík, P Fišer, H Kubátová 12th International On-Line Testing Symposium, 185-186, 2006 | 39 | 2006 |
| Small but nasty logic synthesis examples P Fišer, J Schmidt 8th Int. Workshop on Boolean Problems (IWSBP'08), Freiberg, Germany 18 (19.9 …, 2008 | 32 | 2008 |
| Are XORs in logic synthesis really necessary? I Háleček, P Fišer, J Schmidt 2017 IEEE 20th International Symposium on Design and Diagnostics of …, 2017 | 30 | 2017 |
| FC-Min: A fast multi-output Boolean minimizer P Fišer, J Hlavička, H Kubátová 29th Euromicro Symposium on Digital Systems Design, 451-454, 2003 | 29 | 2003 |
| Flexible two-level boolean minimizer BOOM-II and its applications P Fišer, H Kubátová 9th Euromicro Conference on Digital Systems Design, 369-376, 2006 | 27 | 2006 |
| On logic synthesis of conventionally hard to synthesize circuits using genetic programming P Fišer, J Schmidt, Z Vašíček, L Sekanina 13th IEEE Symposium on Design and Diagnostics of Electronic Systems, 346-351, 2010 | 25 | 2010 |
| Techniques for SAT-based constrained test pattern generation J Balcárek, P Fišer, J Schmidt 14th Euromicro Conference on Digital Systems Design, 360-366, 2011 | 23 | 2011 |
| Test patterns compression technique based on a dedicated SAT-based ATPG J Balcárek, P Fišer, J Schmidt 13th Euromicro Conference on Digital Systems Design, 805-808, 2010 | 23 | 2010 |
| Two-level boolean minimizer BOOM-II P Fišer, H Kubátová Proc. 6th Int. Workshop on Boolean Problems (IWSBP'04), Freiberg, Germany 23 …, 2004 | 23 | 2004 |
| Sources of bias in EDA tools and its influence P Fišer, J Schmidt, J Balcárek 17th International Symposium on Design and Diagnostics of Electronic …, 2014 | 22 | 2014 |
| A fast SOP minimizer for logic funcions described by many product terms P Fišer, D Toman 12th Euromicro Conference on Digital Systems Design, 757-764, 2009 | 21 | 2009 |
| It is better to run iterative resynthesis on parts of the circuit P Fišer, J Schmidt 19th of International Workshop on Logic and Synthesis, 17-24, 2010 | 17 | 2010 |
| An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA P Fišer, P Kubalík, H Kubátová 11th Euromicro Conference on Digital Systems Design, 96-99, 2008 | 17 | 2008 |
| An efficient mixed-mode BIST technique P Fišer, H Kubátová 7th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop …, 2004 | 17 | 2004 |
| Column-matching BIST exploiting test don't-cares P Fišer, J Hlavička, H Kubátová 8th IEEE Europian Test Workshop (ETW), 215-216, 2003 | 17 | 2003 |
| Fast Boolean Minimizer for Completely Specified Functions P Fišer, P Rucký, I Váňová 11th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop …, 2008 | 14 | 2008 |
| Pseudo-random pattern generator design for column-matching BIST P Fišer, H Kubátová 10th Euromicro conference on digital system design architectures, methods …, 2007 | 14 | 2007 |
| A Heuristic method of two-level logic synthesis J Hlavicka, P Fiser The 5th World Multiconference on Systemics, Cybernetics and Informatics, 283-288, 2001 | 14 | 2001 |
Hana KubátováCTU in PragueVerified email at fit.cvut.cz
