| Design of low power two bit magnitude comparator using adiabatic logic D Kumar, M Kumar 2016 International Symposium on Intelligent Signal Processing and …, 2016 | 16 | 2016 |
| Comparative analysis of adiabatic logic challenges for low power CMOS circuit designs D Kumar, M Kumar Microprocessors and Microsystems 60, 107-121, 2018 | 12 | 2018 |
| Implementation of parallel computing and adiabatic logic in full adder design for ultra-low-power applications D Kumar, M Kumar SN Applied Sciences 2 (8), 1388, 2020 | 10 | 2020 |
| An efficient content based image retrieval system for color and shape using optimized K-Means algorithm A Komali, RV Babu, DS Kumar, KG Babu International Journal of Computer Science and Network Security (IJCSNS) 15 …, 2015 | 8 | 2015 |
| A study on adiabatic logic circuits for low power applications A Nandal, D Kumar Int J Eng Res Technol 5 (3), 1-7, 2017 | 7 | 2017 |
| An Approach in Shadow Detection and Reconstruction of Images DS Kumar, M Gargi International Journal of Application or Innovation in Engineering …, 2013 | 7 | 2013 |
| VLSI implementation of wave shaping diode based adiabatic logic (WSDAL) D Kumar, M Kumar International Journal of Electronics 108 (4), 589-606, 2021 | 5 | 2021 |
| Modified 4-2 compressor using improved multiplexer for low power applications D Kumar, M Kumar 2016 International Conference on Advances in Computing, Communications and …, 2016 | 5 | 2016 |
| Signal aware energy efficient approach for low power full adder design with adiabatic logic D Kumar, M Kumar Microsystem Technologies 28 (2), 587-599, 2022 | 3 | 2022 |
| Adiabatic logic-based strong ARM comparator for ultra-low power applications D Kumar, M Kumar Microsystem Technologies 28 (4), 929-936, 2022 | 2 | 2022 |
| Adiabatic logic based full adder design with leakage reduction mechanisms D Kumar, M Kumar Advances in Signal Processing and Communication: Select Proceedings of ICSC …, 2019 | 1 | 2019 |
| Design of low-power full adder using two-phase clocked adiabatic static CMOS logic D Kumar, M Kumar Proceedings of First International Conference on Smart System, Innovations …, 2018 | 1 | 2018 |
| VLSI Implementation of Adiabatic Logic-Based 4× 4 Multiplier for Low Power Applications D Kumar, M Kumar Energy Systems, Drives and Automations: Proceedings of ESDA 2019, 543-551, 2020 | | 2020 |
| Design of Low Power Code Converter using Energy Recovery Logic DKM Kumar International Journal of Control Theory and Applications ISSN :- 0974-5572 …, 2017 | | 2017 |
| Single Bit Low Power Full Adder Cell using Substrate Bias Effect S Semwal, JK Dhanoa, D Kumar | | |
