VAISHALI DHARE
VAISHALI DHARE
Assistant Professor, Nirma University, Institute of Technology, Ahmedabad
Verified email at nirmauni.ac.in
Title
Cited by
Cited by
Year
Defect characterization and testing of QCA devices and circuits: A survey
V Dhare, U Mehta
2015 19th International Symposium on VLSI Design and Test, 1-2, 2015
132015
Multiple Missing Cell Defect Modeling for QCA Devices
MUS Dhare VH
Journal of Electronic Testing 34 (6), 623–641, 2018
62018
Fault analysis of QCA combinational circuit at layout & logic level
V Dhare, U Mehta
2015 IEEE International WIE Conference on Electrical and Computer …, 2015
62015
A Simple Synthesis Process for Combinational QCA Circuits: QSynthesizer
V Dhare, U Mehta
2019 32nd International Conference on VLSI Design and 2019 18th …, 2019
52019
Quantum-dot Cellular Automata (QCA): A Survey
U Mehta, V Dhare
arXiv preprint arXiv:1711.08153, 2017
42017
Development of controllability observability aided combinational ATPG with fault reduction
V Dhare, U Mehta
Recent Trends in Networks and Communications, 682-692, 2010
42010
Single missing cell deposition defect analysis of sequential reversible circuit
V Dhare, U Mehta
2017 Nirma University International Conference on Engineering (NUiCONE), 1-4, 2017
32017
Development of basic fault model and corresponding ATPG for single input missing cell deposition defects in Majority Voter of QCA
UM Vaishali Dhare
2016 IEEE Region 10 Conference (TENCON), 2354 - 2359, 2016
32016
Object Oriented Implementation of Combinational Controllability and Observability Algorithms
VH Dhare, U Mehta
International Journal on Electronics Engineering: Kurukshetra, Hariyana …, 2010
32010
SAF analyses of analog and mixed signal vlsi circuit: Digital to analog converter
V Dhare, U Mehta
International Journal of VLSI Design & Communication Systems (VLSICS) 6 (3), 2015
22015
Implementation of compaction algorithm for ATPG generated partially specified test data
V Dhare, U Mehta
International Journal of VLSI Design & Communication Systems 4 (1), 93, 2013
22013
Test Pattern Generator for Majority Voter based QCA Combinational Circuits targeting MMC Defect
V Dhare, U Mehta
2019 IEEE European Test Symposium (ETS), 1-2, 2019
12019
Defect Analysis of Quantum-dot Cellular Automata Combinational Circuit using HDLQ
V Dhare, U Mehta
International Journal of Advanced Research in Engineering and Technology 7 (2), 2016
12016
Advanced ATPG based on FAN, testability measures and fault reduction
V Dhare, U Mehta
International Journal of VLSI Design & Communication Systems 5 (2), 11, 2014
12014
Implementation and defect analysis of QCA based reversible combinational circuit
V Dhare, D Agarwal
Technologies for Sustainable Development: Proceedings of the 7th Nirma …, 2020
2020
Test Pattern Generator for MV-Based QCA Combinational Circuit Targeting MMC Fault Models
V Dhare, U Mehta
IETE Journal of Research, 1-11, 2019
2019
Logic Optimization Algorithm based on Shannon’s Expansion: Reduction in Area, Power and Delay for Pass Gate Implementation
US Mehta, V Dhare, H Parmar, RA Shah
Journal of VLSI Design Tools & Technology 3 (2), 24-34, 2019
2019
Quantum -dot Cellular Automata (QCA): A Survey
VD Usha Mehta
https://arxiv.org/abs/1711.08153, 2017
2017
Logic Optimization Algorithm based on Shannon’ s Expansion: Reduction in Area, Power and Delay for Pass Gate Implementation
US Mehta, V Dhare, H Parmar, RA Shah
Journal of VLSI Design Tools & Technology 3 (2), 20-30, 2013
2013
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Articles 1–19