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Mitra Purandare
Mitra Purandare
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Verified email at ost.ch
Title
Cited by
Cited by
Year
Interpolant strength
V D’Silva, D Kroening, M Purandare, G Weissenbacher
International Workshop on Verification, Model Checking, and Abstract …, 2010
1252010
Mutation-based test case generation for simulink models
A Brillout, N He, M Mazzucchi, D Kroening, M Purandare, P Rümmer, ...
International Symposium on Formal Methods for Components and Objects, 208-227, 2009
882009
Vacuum cleaning CTL formulae
M Purandare, F Somenzi
International Conference on Computer Aided Verification, 485-499, 2002
772002
Do's and don'ts of CTL state coverage estimation
N Jayakumar, M Purandare, F Somenzi
Proceedings 2003. Design Automation Conference (IEEE Cat. No. 03CH37451 …, 2003
532003
Formal techniques for effective co-verification of hardware/software co-designs
R Mukherjee, M Purandare, R Polig, D Kroening
2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2017
372017
Approximation refinement for interpolation-based model checking
V D’Silva, M Purandare, D Kroening
International Workshop on Verification, Model Checking, and Abstract …, 2008
202008
Coverage in interpolation-based model checking
H Chockler, D Kroening, M Purandare
Design Automation Conference, 182-187, 2010
182010
Method for verifying hardware/software co-designs
M Purandare
US Patent 9,996,637, 2018
82018
Accelerated analysis of Boolean gene regulatory networks
M Purandare, R Polig, C Hagleitner
2017 27th International Conference on Field Programmable Logic and …, 2017
82017
Strengthening properties using abstraction refinement
M Purandare, T Wahl, D Kroening
2009 Design, Automation & Test in Europe Conference & Exhibition, 1692-1697, 2009
82009
EBMC
D Kroening, M Purandare
7
Ebmc: The enhanced bounded model checker
D Kroening, M Purandare
Accessed, 2019
62019
Agile autotuning of a transprecision tensor accelerator overlay for TVM compiler stack
D Diamantopoulos, B Ringlein, M Purandare, G Singh, C Hagleitner
2020 30th International Conference on Field-Programmable Logic and …, 2020
52020
Computing mutation coverage in interpolation-based model checking
H Chockler, D Kroening, M Purandare
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
52012
Restructuring resolution refutations for interpolation
V D’Silva, D Kroening, M Purandare, G Weissenbacher
Technical Report, 2008
52008
Verifying correctness of regular expression transformations that use a post-processor
K Atasu, JR Baumgartner, C Hagleitner, M Purandare
US Patent 8,688,608, 2014
42014
Proving correctness of regular expression accelerators
M Purandare, K Atasu, C Hagleitner
DAC Design Automation Conference 2012, 350-355, 2012
42012
System and method for emulating a logic circuit design using programmable logic devices
M Desai, M Purandare, H Sharma, S Patkar
US Patent App. 11/207,559, 2006
42006
Fpga accelerated analysis of boolean gene regulatory networks
M Manica, R Polig, M Purandare, R Mathis, C Hagleitner, MR Martinez
IEEE/ACM Transactions on Computational Biology and Bioinformatics 17 (6 …, 2019
32019
Deep neural network on field-programmable gate array
M Purandare, D Diamantopoulos, R Polig
US Patent App. 16/558,446, 2021
22021
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