| Layered T full adder using Quantum-dot Cellular Automata C Mukherjee, AS Sukla, SS Basu, R Chakrabarty, A Khan, D De 2015 IEEE International Conference on Electronics, Computing and …, 2015 | 22 | 2015 |
| T-Gate: Concept of partial polarization in Quantum Dot Cellular Automata C Mukherjee, SS Roy, S Panda, B Maji 2016 20th International Symposium on VLSI Design and Test (VDAT), 1-6, 2017 | 18 | 2017 |
| Layered T comparator design using quantum-dot cellular automata SS Roy, C Mukherjee, S Panda, AK Mukhopadhyay, B Maji Devices for Integrated Circuit (DevIC), 2017, 2017 | 16 | 2017 |
| Computational Advancement in Communication Circuits and Systems I Sarkar, S Goswami, P Majumder Springer, New Delhi, 2020 | 15* | 2020 |
| Effect of temperature and kink energy in multilevel digital circuit using Quantum dot cellular automata R Chakraborty, D De, A Khan, C Mukherjee, S Pramanik 2012 5th International Conference on Computers and Devices for Communication …, 2012 | 14 | 2012 |
| Synthesis of Standard Functions and Generic Ex-OR Module Using Layered T Gate C Mukherjee, S Panda, AK Mukhopadhyay, B Maji International Journal of High Performance Systems Architecture 7 (2), 70-86, 2017 | 13 | 2017 |
| QCA gray code converter circuits using LTEx methodology C Mukherjee, S Panda, AK Mukhopadhyay, B Maji International Journal of Theoretical Physics 57, 2068-2092, 2018 | 11 | 2018 |
| Towards modular binary to gray converter design using LTEx module of quantum-dot cellular automata C Mukherjee, S Panda, AK Mukhopadhyay, B Maji Microsystem Technologies 25, 2011-2018, 2019 | 9 | 2019 |
| Decoder segment optimization of ROM design in quantum dot cellular automata DD Mukherjee Chiradeep,Pramanik Sayak ,Chakraborty Ratna High Performance Computing and Applications (ICHPCA), 2014 International …, 2014 | 8* | 2014 |
| Introducing Galois field polynomial addition in quantum-dot cellular automata C Mukherjee, S Panda, AK Mukhopadhyay, B Maji Applied Nanoscience 9, 2127-2146, 2019 | 6 | 2019 |
| Utilization of LTEx Feynman Gate in Designing the QCA based Reversible Binary to Gray and Gray to Binary Code Converters C Mukherjee, S Panda, AK Mukhopadhyay, B Maji Micro and Nanosystems 12 (1), 2020 | 5 | 2020 |
| Majority-layered T hybridization using quantum-dot cellular automata C Mukherjee, S Panda, AK Mukhopadhyay, B Maji Cogent Engineering 4 (1), 1286732, 2017 | 5 | 2017 |
| Implementation of Toffoli Gate Using LTEx Module of Quantum-Dot Cellular Automata C Mukherjee, D Ghosh, S Halder, SN Surai, S Panda, AK Mukhopadhyay, ... Proceedings of Contemporary Advances in Innovative and Applicable …, 2018 | 4 | 2018 |
| A comparative study of vein pattern recognition for biometrie authentication H Thakuria, A Dutta, A Sarkar, A Ghosal, R Saha, S Pramanik, S Mitra, ... 2017 8th IEEE Annual Information Technology, Electronics and Mobile …, 2017 | 4 | 2017 |
| FPGA based effecient architecture for conversion of binay to residue number system UN Thakur, S Mallick, RM Moitra, M Kotal, S Zakaria, A Chakraborty, ... 2017 8th IEEE Annual Information Technology, Electronics and Mobile …, 2017 | 4 | 2017 |
| Layered T methodology in QCA: NAND/NOR based circuit designing approach C Mukherjee, S Pramanik, DS Roy, S Mondal, A Sinha, AG Roy, S Bid, ... 2016 IEEE 7th Annual Ubiquitous Computing, Electronics & Mobile …, 2016 | 4 | 2016 |
| The design, analysis, and cost estimation of a generic adder and subtractor using the layered T (LT) logic reduction methodology with a quantum-dot cellular-automata-based approach C Mukherjee, S Panda, AK Mukhopadhyay, B Maji Journal of Computational Electronics 20 (4), 1611-1624, 2021 | 3 | 2021 |
| Generic parity generators design using LTEx methodology: A quantum-dot cellular automata based approach C Mukherjee, S Panda, AK Mukhopadhyay, B Maji International Journal of Nano Dimension 9 (3), 215-227, 2018 | 3 | 2018 |
| Search of appropriate semiconductor for PIN Diode fabrication in terms of resistance analysis A Aditya, S Khandelwal, C Mukherjee, A Khan, S Panda, B Maji 2015 International Conference on Recent Developments in Control, Automation …, 2015 | 3 | 2015 |
| QCA Realization of Reversible Gates Using Layered T Logic Reduction Technique C Mukherjee, S Panda, AK Mukhopadhyay, B Maji 2019 Devices for Integrated Circuit (DevIC), 167-171, 2019 | 2 | 2019 |
Dr. Asish K MukhopadhyayEx-Professor Emeritus, IET, Bundelkhand University, Jhansi ; Former Group Director, SRGI, Jhansi;Verified email at srgi.ac.in
