Jawar Singh, Ph.D.
Jawar Singh, Ph.D.
Professor, Electrical Engineering Department, Indian Institute of Technology Patna
Verified email at - Homepage
Cited by
Cited by
Charge-Plasma Based Process Variation Immune Junctionless Transistor
C Sahu, J Singh
IEEE Electron Device Letters 35 (3), 411 - 413, 2014
Experimental demonstration of 100nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and …
S Mookerjea, D Mohata, R Krishnan, J Singh, A Vallett, A Ali, T Mayer, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-3, 2009
Robust SRAM Designs and Analysis
J Singh, SP Mohanty, D Pradhan
Springer Science & Business Media, 2012
A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3 V VDD applications
J Singh, K Ramakrishnan, S Mookerjea, S Datta, N Vijaykrishnan, ...
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 181-186, 2010
Potential benefits and sensitivity analysis of dopingless transistor for low power applications
C Sahu, J Singh
IEEE Transactions on Electron Devices 62 (3), 729-735, 2015
A single ended 6 T SRAM cell design for ultra-low-voltage applications
J Singh, DK Pradhan, S Hollis, SP Mohanty
IEICE Electronics Express 5 (18), 750-755, 2008
Realization of efficient RF energy harvesting circuits employing different matching technique
S Agrawal, SK Pandey, J Singh, MS Parihar
Fifteenth International Symposium on Quality Electronic Design, 754-761, 2014
PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET
A Lahgere, C Sahu, J Singh
IEEE Transactions on Electron Devices 62 (8), 6, 2015
Blockchain-based Interoperable Healthcare Using Zero-knowledge Proofs and Proxy Re-Encryption
B Sharma, R Halder, J Singh
2020 IEEE International Conference on COMmunication Systems &NETworkS …, 2020
Memristor based unbalanced ternary logic gates
M Khalid, J Singh
Analog Integrated Circuits and Signal Processing 87, 399-406, 2016
Investigating the impact of NBTI on different power saving cache strategies
A Ricketts, J Singh, K Ramakrishnan, N Vijaykrishnan, DK Pradhan
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010 …, 2010
An Electrically Doped Dynamically Configurable Field Effect Transistor for Low Power and High Performance Applications
A Lahgere, C Sahu, J Singh
IET Electronics Letters, 2, 2015
Design and performance projection of symmetric bipolar charge-plasma transistor on SOI
C Sahu, A Ganguly, J Singh
Electronics Letter, 2014
Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs
A Lahgere, M Panchore, J Singh
Superlattices and Microstructures 96, 16-25, 2016
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies
J Singh, J Mathew, DK Pradhan, SP Mohanty
2008 IEEE International SOC Conference, 243-246, 2008
Temperature sensitivity analysis of dopingless charge-plasma transistor
V Shrivastava, A Kumar, C Sahu, J Singh
Solid-State Electronics 117, 94-99, 2016
A 0.6 V, low-power and high-gain ultra-wideband low-noise amplifier with forward-body-bias technique for low-voltage operations
S Pandey, J Singh
IET Microwaves, Antennas & Propagation 9 (8), 728-734, 2015
Device and circuit performance analysis of double gate junctionless transistors at L g= 18 nm
C Sahu, J Singh
IEEE/IET The Journal of Engineering 1 (1), 2014
Single ended 6T SRAM with isolated read-port for low-power embedded systems
J Singh, DK Pradhan, S Hollis, SP Mohanty, J Mathew
2009 Design, Automation & Test in Europe Conference & Exhibition, 917-922, 2009
Computer aided analysis of phonocardiogram
J Singh, RS Anand
Journal of Medical Engineering & Technology 31 (5), 319-323, 2007
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