| Effect of band-to-band tunneling on junctionless transistors S Gundapaneni, M Bajaj, RK Pandey, KVRM Murali, S Ganguly, ... IEEE Transactions on Electron Devices 59 (4), 1023-1029, 2012 | 206 | 2012 |
| A Tunnel FET forScaling Below 0.6 V With a CMOS-Comparable Performance R Asra, M Shrivastava, KVRM Murali, RK Pandey, H Gossner, VR Rao IEEE Transactions on Electron Devices 58 (7), 1855-1863, 2011 | 172 | 2011 |
| Direct selective laser sintering of iron–graphite powder mixture K Murali, AN Chatterjee, P Saha, R Palai, S Kumar, SK Roy, PK Mishra, ... Journal of Materials Processing Technology 136 (1-3), 179-185, 2003 | 106 | 2003 |
| Probing decoherence with electromagnetically induced transparency in superconductive quantum circuits K Murali, Z Dutton, WD Oliver, DS Crankshaw, TP Orlando Physical review letters 93 (8), 087003, 2004 | 98 | 2004 |
| Quantum-information processing by nuclear magnetic resonance: Experimental implementation of half-adder and subtractor operations using an oriented spin-7/2 system K Murali, N Sinha, TS Mahesh, MH Levitt, KV Ramanathan, A Kumar Physical Review A 66 (2), 022313, 2002 | 73 | 2002 |
| CMOS logic device and circuit performance of Si gate all around nanowire MOSFET K Nayak, M Bajaj, A Konar, PJ Oldiges, K Natori, H Iwai, KVRM Murali, ... IEEE Transactions on Electron Devices 61 (9), 3066-3074, 2014 | 60 | 2014 |
| Carrier transport in high mobility InAs nanowire junctionless transistors A Konar, J Mathew, K Nayak, M Bajaj, RK Pandey, S Dhara, KVRM Murali, ... Nano letters 15 (3), 1684-1690, 2015 | 52 | 2015 |
| Random dopant fluctuation induced variability in undoped channel Si gate all around nanowire n-MOSFET K Nayak, S Agarwal, M Bajaj, KVRM Murali, VR Rao IEEE Transactions on Electron Devices 62 (2), 685-688, 2015 | 51 | 2015 |
| Electromagnetically induced transparency in superconducting quantum circuits: Effects of decoherence, tunneling, and multilevel crosstalk Z Dutton, K Murali, WD Oliver, TP Orlando Physical Review B 73 (10), 104516, 2006 | 50 | 2006 |
| Scheduling cost efficient datacenter load distribution AN Chatterjee, HF Hamann, KM Shankar, S Lu, KVRM Murali US Patent 9,654,414, 2017 | 49 | 2017 |
| Trap generation in IL and HK layers during BTI/TDDB stress in scaled HKMG N and P MOSFETs S Mukhopadhyay, K Joshi, V Chaudhary, N Goel, S De, RK Pandey, ... 2014 IEEE International Reliability Physics Symposium, GD. 3.1-GD. 3.11, 2014 | 40 | 2014 |
| Nanotechnology for energy sustainability, 3 volume set B Raj, M Van de Voorde, Y Mahajan John Wiley & Sons, 2017 | 38 | 2017 |
| Effect of meso-structure on strength and size effect in concrete under compression S Rangari, K Murali, A Deb Engineering Fracture Mechanics 195, 162-185, 2018 | 37 | 2018 |
| Metal-gate granularity-induced threshold voltage variability and mismatch in Si gate-all-around nanowire n-MOSFETs K Nayak, S Agarwal, M Bajaj, PJ Oldiges, KVRM Murali, VR Rao IEEE Transactions on Electron Devices 61 (11), 3892-3895, 2014 | 36 | 2014 |
| A binary tunnel field effect transistor with a steep sub-threshold swing and increased on current R Asra, KVRM Murali, VR Rao Japanese Journal of Applied Physics 49 (12R), 120203, 2010 | 35 | 2010 |
| A comprehensive DC/AC model for ultra-fast NBTI in deep EOT scaled HKMG p-MOSFETs N Goel, S Mukhopadhyay, N Nanaware, S De, RK Pandey, K Murali, ... 2014 IEEE International Reliability Physics Symposium, 6A. 4.1-6A. 4.12, 2014 | 31 | 2014 |
| On the Electron and Hole Tunneling in aGate Stack With Extreme Interfacial-Layer Scaling T Ando, ND Sathaye, KVRM Murali, EA Cartier IEEE electron device letters 32 (7), 865-867, 2011 | 29 | 2011 |
| Crystallographic-orientation-dependent gate-induced drain leakage in nanoscale MOSFETs RK Pandey, KVRM Murali, SS Furkay, PJ Oldiges, EJ Nowak IEEE transactions on electron devices 57 (9), 2098-2105, 2010 | 29 | 2010 |
| A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs T Yamashita, S Mehta, VS Basker, R Southwick, A Kumar, ... 2015 Symposium on VLSI Technology (VLSI Technology), T154-T155, 2015 | 27 | 2015 |
| Field effect transistor having phase transition material incorporated into one or more components for reduced leakage current KVRM Murali, EJ Nowak, SP Parkin US Patent 8,896,035, 2014 | 25 | 2014 |
Mohit BajajSynopsysVerified email at synopsys.com
