| A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits B Varaprasad, LM Patnaik, HS Jamadagni, VK Agrawal IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 40 | 2004 |
| A review on printed electronics with digital 3D printing: fabrication techniques, materials, challenges and future opportunities CH Rao, K Avinash, B Varaprasad, S Goel Journal of Electronic Materials 51 (6), 2747-2765, 2022 | 38 | 2022 |
| A new ATPG technique (ExpoTan) for testing analog circuits B Varaprasad, LM Patnaik, HS Jamadagni, VK Agrawal IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 29 | 2006 |
| Rule-based design for multiple nodes upset tolerant latch architecture FM Sajjade, NK Goyal, B Varaprasad IEEE Transactions on Device and Materials Reliability 19 (4), 680-687, 2019 | 18 | 2019 |
| Plasma treatment and copper metallization for reliable plated-through-holes in microwave PCBS for space electronic packaging A Kothuru, AP Singh, B Varaprasad, S Goel IEEE Transactions on Components, Packaging and Manufacturing Technology 10 …, 2020 | 15 | 2020 |
| Radiation hardened by design latches—A review and SEU fault simulations FM Sajjade, NK Goyal, B Varaprasad, R Moogina Microelectronics Reliability 83, 127-135, 2018 | 11 | 2018 |
| Single event transient (SET) mitigation circuits with immune leaf nodes FM Sajjade, NK Goyal, B Varaprasad IEEE Transactions on Device and Materials Reliability 21 (1), 70-78, 2021 | 9 | 2021 |
| Plasma-generated etchback to improve the via-reliability in high-Tg substrates used in multilayer PWBs for space electronic packaging AP Singh, M Saravanan, B Varaprasad IEEE Transactions on Components, Packaging and Manufacturing Technology 6 (6 …, 2016 | 9 | 2016 |
| The state of VLSI testing LM Patnaik, HS Jamadagni, VK Agrawal, B Varaprasad IEEE potentials 21 (3), 12-16, 2002 | 7 | 2002 |
| Direct ink writing as an eco-friendly PCB manufacturing technique for rapid prototyping B Varaprasad, S Goel 2021 Fourth International Conference on Electrical, Computer and …, 2021 | 4 | 2021 |
| A survey on test point insertion (TPI) Schemes K Padmapriya, B Varaprasad, N Varalakshmi 2020 International Conference on Inventive Computation Technologies (ICICT …, 2020 | 3 | 2020 |
| Hi-reI ASIC Design and Development-A Case Study K Padmapriya, B Varaprasad, V Lekshmi, S Sudhakar, S Udupa, G Sarkar, ... 2018 Second International Conference on Electronics, Communication and …, 2018 | 3 | 2018 |
| Testing of analog circuits-Built in self test B Varaprasad | 3 | 2009 |
| REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture Raghunandana, B Varaprasad, R Sonza, S Virendra IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022 | 2 | 2022 |
| Configurable Drive Scheme for Stepper Motors in Space Application V Lekshmi, B Varaprasad, GN Sonal, TS Vishnu 2022 First International Conference on Electrical, Electronics, Information …, 2022 | 2 | 2022 |
| Automation of Translating Unit-Level Verification Scenarios for Test Vector Generation of SoC R Anilkumar, B Varaprasad, K Padmapriya Intelligent Sustainable Systems: Selected Papers of WorldS4 2021, Volume 1 …, 2022 | 2 | 2022 |
| Improving test coverage of hi-reliability ASIC designs with test point insertion for space applications K Padmapriya, B Varaprasad 2020 International Conference on Smart Electronics and Communication (ICOSEC …, 2020 | 2 | 2020 |
| ASIC Development in ISAC B Varaprasad, K Parameswaran Journal of Spacecraft Technology 21 (1), 79-84, 2011 | 2 | 2011 |
| An Efficient Test Pattern Generation Scheme for an On Chip BIST B Varaprasad, LM Patnaik, HS Jamadagni, VK Agrawal VLSI Design 12 (4), 551-562, 2001 | 2 | 2001 |
| TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture KK Raghunandana, V BKSVL, MS Reorda, V Singh 2023 IEEE 29th International Symposium on On-Line Testing and Robust System …, 2023 | 1 | 2023 |
