| Decimal multiplication using compact BCD multiplier RK James, TK Shahana, KP Jacob, S Sasi 2008 International Conference on Electronic Design, 1-6, 2008 | 42 | 2008 |
| Polyphase implementation of non-recursive comb decimators for sigma-delta A/D converters TK Shahana, RK James, BR Jose, KP Jacob, S Sasi 2007 IEEE Conference on Electron Devices and Solid-State Circuits, 825-828, 2007 | 39 | 2007 |
| Fault tolerant error coding and detection using reversible gates RK James, KP Jacob, S Sasi TENCON 2007-2007 IEEE Region 10 Conference, 1-4, 2007 | 32 | 2007 |
| Performance analysis of FIR digital filter design: RNS versus traditional TK Shahana, RK James, BR Jose, KP Jacob, S Sasi 2007 International Symposium on Communications and Information Technologies, 1-5, 2007 | 31 | 2007 |
| A new look at reversible logic implementation of decimal adder RK James, TK Shahana, KP Jacob, S Sasi 2007 International Symposium on System-on-Chip, 1-4, 2007 | 20 | 2007 |
| Performance analysis of double digit decimal multiplier on various FPGA logic families RK James, KP Jacob, S Sasi 2009 5th Southern Conference on Programmable Logic (SPL), 165-170, 2009 | 15 | 2009 |
| System, method and program product for local client device context-aware shared resource and service management MD De Assuncao, RK James, FL Koch, MAS Netto US Patent App. 13/534,316, 2014 | 13 | 2014 |
| Token based detection and neural network based reconstruction framework against code injection vulnerabilities TK George, KP Jacob, RK James Journal of Information Security and Applications 41, 75-91, 2018 | 12 | 2018 |
| Genetic algorithm based design of combinational logic circuits using universal logic modules CK Vijayakumari, P Mythili, RK James, CVA Kumar Procedia Computer Science 46, 1246-1253, 2015 | 12 | 2015 |
| Optimal design of combinational logic circuits using genetic algorithm and Reed-Muller universal logic modules CK Vijayakumari, P Mythili, RK James, SA Kumar 2014 International Conference on Embedded Systems (ICES), 1-6, 2014 | 12 | 2014 |
| Reversible binary coded decimal adders using toffoli gates RK James, K Poulose Jacob, S Sasi Advances in Computational Algorithms and Data Analysis, 117-131, 2009 | 11 | 2009 |
| Design of compact reversible decimal adder using RPS gates RK James, S Sasi 2012 World Congress on Information and Communication Technologies, 344-349, 2012 | 10 | 2012 |
| Traffic aware routing in 3D NoC using interleaved asymmetric edge routers RG Kunthara, RK James, SZ Sleeba, J Jose Nano Communication Networks 27, 100334, 2021 | 9 | 2021 |
| RNS based programmable multi-mode decimation filter for WCDMA and WiMAX TK Shahana, BR Jose, RK James, KP Jacob, S Sasi VTC Spring 2008-IEEE Vehicular Technology Conference, 1831-1835, 2008 | 9 | 2008 |
| Improved reversible logic implementation of decimal adder R James, TK Shahana, KP Jacob, S Sasi IEEE 11th VDAT Symposium Aug 8 (11), 2007 | 9 | 2007 |
| High performance, low latency double digit decimal multiplier on ASIC and FPGA RK James, KP Jacob, S Sasi 2009 World Congress on Nature & Biologically Inspired Computing (NaBIC …, 2009 | 7 | 2009 |
| Dual-mode RNS based programmable decimation filter for WCDMA and WLANa TK Shahana, BR Jose, RK James, KP Jacob, S Sasi 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 952-955, 2008 | 7 | 2008 |
| Fast reversible binary coded decimal adders RK James, KP Jacob, S Sasi International Journal of electrical and electronics engineering 4 (3), 254-266, 2008 | 7 | 2008 |
| Enhancement and modeling of drain current in negative capacitance double gate TFET RK James, J Jacob, A Pradeep Silicon 14 (11), 6157-6167, 2022 | 6 | 2022 |
| ReDC: reduced deflection CHIPPER router for bufferless NoCs RG Kunthara, RK James, SZ Sleeba, J Jose 2018 8th International Symposium on Embedded Computing and System Design …, 2018 | 6 | 2018 |
Dr. Poulose Jacob K.Professor of Computer Science & Pro VC - Emeritus, COCHIN University of Science & TechnologyVerified email at cusat.ac.in
