Madhura Purnaprajna
Madhura Purnaprajna
Associate Professor, Amrita School of Engineering
Verified email at blr.amrita.edu
TitleCited byYear
Genetic algorithms for hardware–software partitioning and optimal resource allocation
M Purnaprajna, M Reformat, W Pedrycz
Journal of Systems Architecture 53 (7), 339-354, 2007
642007
ASIC implementation of a high speed WGNG for communication channel emulation [white Gaussian noise generator]
E Fung, K Leung, N Parimi, M Purnaprajna, VC Gaudet
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004., 304-309, 2004
232004
Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case
G Falcao, M Owaida, D Novo, M Purnaprajna, N Bellas, CD Antonopoulos, ...
2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012
212012
Power aware reconfigurable multiprocessor for elliptic curve cryptography
M Purnaprajna, C Puttmann, M Porrmann
2008 Design, Automation and Test in Europe, 1462-1467, 2008
182008
Making wide-issue VLIW processors viable on FPGAs
M Purnaprajna, P Ienne
ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-16, 2012
172012
Self-optimization of mpsocs targeting resource efficiency and fault tolerance
M Porrmann, M Purnaprajna, C Puttmann
2009 NASA/ESA Conference on Adaptive Hardware and Systems, 467-473, 2009
162009
Compiler-driven reconfiguration of multiprocessors
M Hußmann, M Thies, U Kastens, M Purnaprajna, M Porrmann, U Rückert
Proceedings of the Workshop on Application Specific Processors (WASP) 2007, 2007
112007
Enhancing design space exploration by extending CPU/GPU specifications onto FPGAs
M Owaida, G Falcao, J Andrade, C Antonopoulos, N Bellas, ...
ACM Transactions on Embedded Computing Systems (TECS) 14 (2), 1-23, 2015
92015
A case for heterogeneous technology-mapping: Soft versus hard multiplexers
M Purnaprajna, P Ienne
2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013
92013
Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions
M Belwal, M Purnaprajna, TSB Sudarshan
2015 25th International Conference on Field Programmable Logic and …, 2015
82015
Shadow and-inverter cones
H Parandeh-Afshar, G Zgheib, D Novo, M Purnaprajna, P Ienne
2013 23rd International Conference on Field programmable Logic and …, 2013
82013
Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis
M Purnaprajna, M Porrmann, U Rueckert, M Hussmann, M Thies, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 3 (3), 1-25, 2010
52010
Run-time reconfigurable multiprocessors
M Purnaprajna
University of Paderborn, 2010
42010
Tilenet: Scalable architecture for high-throughput ternary convolution neural networks using fpgas
SS Vikram, V Pant, M Mody, M Purnaprajna
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
32018
Shadow AICs: Reaping the benefits of And-Inverter Cones with minimal architectural impact
H Parandeh-Afshar, G Zgheib, D Novo, M Purnaprajna, P Ienne
Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2013
32013
Run-time reconfigurability in embedded multiprocessors
M Purnaprajna, M Porrmann, U Rueckert
ACM SIGARCH Computer Architecture News 37 (2), 30-37, 2009
32009
Using run-time reconfiguration for energy savings in parallel data processing
M Purnaprajna, C Pohl, M Porrmann, U Rueckert
Proceedings of the International Conference on Engineering of Reconfigurable …, 2009
32009
Recurrent neural networks: an embedded computing perspective
NM Rezk, M Purnaprajna, T Nordström, Z Ul-Abdin
arXiv preprint arXiv:1908.07062, 2019
12019
Work in Progress: Performance Modeling for Data Distribution in Heterogeneous Computing Systems
K Vanishree, M Purnaprajna
2018 International Conference on Compilers, Architectures and Synthesis for …, 2018
12018
Optimized allocation of tasks in heterogeneous computing systems
M Purnaprajna, V Kattishetti
US Patent App. 16/108,647, 2019
2019
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Articles 1–20