| A low-power circuit technique for domino CMOS logic P Meher, KK Mahapatra 2013 International Conference on Intelligent Systems and Signal Processing …, 2013 | 14 | 2013 |
| Modifications in CMOS dynamic logic style: a review paper P Meher, K Mahapatra Journal of The Institution of Engineers (India): Series B 96, 391-399, 2015 | 12 | 2015 |
| Statistical analysis of target tracking algorithms in thermal imagery U Gupta, P Meher Cognitive Informatics and Soft Computing: Proceeding of CISC 2019, 635-646, 2020 | 11 | 2020 |
| Low power noise tolerant domino 1-bit full adder P Meher, KK Mahapatra 2014 International Conference on Advances in Energy Conversion Technologies …, 2014 | 11 | 2014 |
| A high speed low noise CMOS dynamic full adder cell P Meher, KK Mahapatra 2013 International conference on Circuits, Controls and Communications …, 2013 | 10 | 2013 |
| A technique to increase noise-tolerance in dynamic digital circuits P Meher, KK Mahapatra 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics …, 2012 | 9 | 2012 |
| Ultralow power, noise immune stacked‐double stage clocked‐inverter domino technique for ultradeep submicron technology SR Ghimiray, P Meher, PK Dutta International Journal of Circuit Theory and Applications 46 (11), 1953-1967, 2018 | 7 | 2018 |
| An improved charge‐sharing elimination pseudo‐domino logic SR Ghimiray, P Meher, PK Dutta International Journal of Circuit Theory and Applications 48 (8), 1346-1362, 2020 | 6 | 2020 |
| Design of high frequency D flip flop circuit for phase detector application SK Saw, P Meher, SK Chakraborty TENCON 2017-2017 IEEE Region 10 Conference, 229-233, 2017 | 6 | 2017 |
| Ultra low-power and noise tolerant CMOS dynamic circuit technique P Meher, KK Mahapatra TENCON 2011-2011 IEEE Region 10 Conference, 1175-1179, 2011 | 6 | 2011 |
| A new ultra low-power and noise tolerant circuit technique for CMOS domino logic P Meher, KK Mahapatra | 6 | 2011 |
| Effect of Ni on microstructure, mechanical property of mechanically alloyed W-Ni-Nb P Meher, C Kiran, A Patra, R Saxena, SK Karak Materials Today: Proceedings 18, 765-773, 2019 | 5 | 2019 |
| High speed and low power dynamic logic style P Meher, KK Mahapatra International Journal of VLSI and Embedded Systems 2 (3), 313-7, 2013 | 5 | 2013 |
| Efficient VLSI implementation of CORDIC-based multiplier architecture R Baruah, P Meher, AK Pradhan Information Systems Design and Intelligent Applications: Proceedings of …, 2019 | 3 | 2019 |
| Design of differential amplifier using current mirror load in 90 nm CMOS technology P Das, SK Saw, P Meher Information Systems Design and Intelligent Applications: Proceedings of …, 2019 | 3 | 2019 |
| Design and implementation of TG based D flip flop for clock and data recovery application SK Saw, M Maiti, P Meher, SK Chakraborty IET Digital Library, 2016 | 3 | 2016 |
| A high-performance circuit technique for CMOS dynamic logic P Meher, KK Mahapatra 2011 IEEE Recent Advances in Intelligent Computational Systems, 338-342, 2011 | 3 | 2011 |
| Electronic Systems and Intelligent Computing Proceedings of ESIC 2020 PK Mallick, P Meher, A Majumder, SK Das Proceedings of ESIC, 1, 2020 | 2 | 2020 |
| Design and Analysis of Dual Modulus Prescaler Circuit for Frequency Synthesizer SK Saw, M Maiti, P Meher 2019 IEEE International Symposium on Smart Electronic Systems (iSES …, 2019 | 2 | 2019 |
| Energy efficient, noise immune 4× 4 Vedic multiplier using semi-domino logic style SR Ghimiray, P Meher, PK Dutta TENCON 2017-2017 IEEE Region 10 Conference, 1037-1041, 2017 | 2 | 2017 |
