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Mukesh Agrawal
Mukesh Agrawal
Verified email at intel.com
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Year
Scan based side channel attacks on stream ciphers and their counter-measures
M Agrawal, S Karmakar, D Saha, D Mukhopadhyay
International Conference on Cryptology in India, 226-238, 2008
742008
Power level distributions of radio base station equipment and user devices in a 3G mobile communication network in India and the impact on assessments of realistic RF EMF exposure
P Joshi, M Agrawal, B Thors, D Colombi, A Kumar, C T÷rnevik
IEEE Access 3, 1051-1059, 2015
272015
Test-cost modeling and optimal test-flow selection of 3-D-stacked ICs
M Agrawal, K Chakrabarty
IEEE Transactions on Computer-Aided Design of Integrated Circuits andá…, 2015
272015
Test-time optimization in NOC-based manycore SOCs using multicast routing
M Agrawal, K Chakrabarty
VLSI Test Symposium (VTS), 2014 IEEE 32nd, 1-6, 2014
252014
Test-cost optimization and test-flow selection for 3D-stacked ICs
M Agrawal, K Chakrabarty
VLSI Test Symposium (VTS), 2013 IEEE 31st, 1-6, 2013
222013
Test and design-for-testability solutions for 3D integrated circuits
K Chakrabarty, M Agrawal, S Deutsch, B Noia, R Wang, F Ye
IPSJ Transactions on System LSI Design Methodology 7, 56-73, 2014
192014
A dynamic programming solution for optimizing test delivery in multicore SOCs
M Agrawal, M Richter, K Chakrabarty
Test Conference (ITC), 2012 IEEE International, 1-10, 2012
192012
Test-Delivery Optimization in Manycore SOCs
M Agrawal, M Richter, K Chakrabarty
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactionsá…, 2014
122014
Sealing device and positioning device using the same
T Nakamura, N Saji
US Patent App. 10/013,352, 2002
9*2002
Reuse-based optimization for prebond and post-bond testing of 3-D-stacked ICs
M Agrawal, K Chakrabarty, R Widialaksono
IEEE Transactions on Computer-Aided Design of Integrated Circuits andá…, 2014
72014
Simultaneous task scheduling and resource binding for digital print automation
M Agrawal, K Chakrabarty, J Zeng, IJ Lin, G Dispoto
IIE Annual Conference. Proceedings, 1, 2011
72011
Digital print workflow optimization under due-dates, opportunity cost and resource constraints
M Agrawal, Q Duan, K Chakrabarty, J Zeng, IJ Lin, G Dispoto, YS Lee
2011 9th IEEE International Conference on Industrial Informatics, 86-92, 2011
52011
Micro-sector cache: improving space utilization in sectored DRAM caches
M Chaudhuri, M Agrawal, J Gaur, S Subramoney
ACM Transactions on Architecture and Code Optimization (TACO) 14 (1), 1-29, 2017
42017
A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs
M Agrawal, K Chakrabarty, B Eklow
IEEE Transactions on Computer-Aided Design of Integrated Circuits andá…, 2015
32015
The hype, myths, and realities of testing 3D integrated circuits
R Wang, S Deutsch, M Agrawal, K Chakrabarty
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016
22016
A distributed, reconfigurable, and reusable bist infrastructure for 3D-stacked ICs
M Agrawal, K Chakrabarty, B Eklow
2014 International Test Conference, 1-10, 2014
22014
2015 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 34
G Agosta, M Agrawal, N Ahmed, M Ahrens, VB Ajabshir, F Akopyan, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits andá…, 2015
2015
Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs
M Agrawal
Duke University, 2014
2014
A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICs
M Agrawal, K Chakrabarty
Test Conference (ITC), 2013 IEEE International, 1-10, 2013
2013
Real-Time and Online Digital-Print Factory Workflow Optimization
Q Duan, M Agrawal, K Chakrabarty, J Zeng, G Dispoto
2012
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