| Metal and silicon containing capping layers for interconnects J Yu, G Jiang, P Subramonium, R Shaviv, HJ Wu, N Shankar US Patent 8,753,978, 2014 | 397 | 2014 |
| Etching substrates using ale and selective deposition S Tan, J Yu, R Wise, N Shamma, Y Pan US Patent 10,269,566, 2019 | 132 | 2019 |
| Predicting synergy in atomic layer etching KJ Kanarik, S Tan, W Yang, T Kim, T Lill, A Kabansky, EA Hudson, T Ohba, ... Journal of Vacuum Science & Technology A 35 (5), 2017 | 111 | 2017 |
| Interfacial capping layers for interconnects J Yu, HJ Wu, G Dixit, B Van Schravendijk, P Subramonium, G Jiang, ... US Patent 8,268,722, 2012 | 69 | 2012 |
| MOCVD growth of non-epitaxial and epitaxial ZnS thin films J Fang, PH Holloway, JE Yu, KS Jones, B Pathangey, E Brettschneider, ... Applied Surface Science 70, 701-706, 1993 | 61 | 1993 |
| Biased H2 etch process in deposition-etch-deposition gap fill W Zhu, J Yu, S Sutanto, P Sun, JCH Lowe, W Fung, TW Poon US Patent 7,163,896, 2007 | 34 | 2007 |
| Tin oxide films in semiconductor device manufacturing J Yu, S Tan, Y Jiang, HJ Wu, R Wise, Y Pan, N Shamma, B Volosskiy US Patent 10,546,748, 2020 | 31 | 2020 |
| Eliminating yield impact of stochastics in lithography N Shamma, R Wise, J Yu, S Tan US Patent 10,796,912, 2020 | 24 | 2020 |
| Atomic layer etching for enhanced bottom-up feature fill S Tan, KIM Taeseung, J Yu, P Nalla, N Tjokro, A Kolics, KJ Kanarik US Patent 9,837,312, 2017 | 24 | 2017 |
| Advanced metallization scheme for 3× 50µm via middle TSV and beyond S Van Huylenbroeck, Y Li, N Heylen, K Croes, G Beyer, E Beyne, M Brouri, ... 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 66-72, 2015 | 20 | 2015 |
| Modeling ion implantation of HgCdTe HG Robinson, DH Mao, BL Williams, S Holander-Gleixner, JE Yu, ... Journal of Electronic Materials 25 (8), 1336-1340, 1996 | 20 | 1996 |
| Stress profile modulation in STI gap fill J Yu, CI Lang, JH Huang US Patent 7,482,245, 2009 | 18 | 2009 |
| Systems and methods to retard copper diffusion and improve film adhesion for a dielectric barrier on copper J Yu, KS Wong, S Jain, S Nag, H Fu, A Gupta, BJ Van Schravendijk US Patent 6,764,952, 2004 | 15 | 2004 |
| Tin oxide mandrels in patterning J Yu, SSH Tan, S Heo, B Volosskiy, SK Kanakasabapathy, R Wise, Y Pan, ... US Patent 11,355,353, 2022 | 14 | 2022 |
| Integrated approach to improving local CD uniformity in EUV patterning A Liang, J Hermans, T Tran, K Viatkina, CW Liang, B Ward, S Chuang, ... Extreme Ultraviolet (EUV) Lithography VIII 10143, 251-265, 2017 | 14 | 2017 |
| Advanced integrated metallization enables 3D-IC TSV scaling J Yu, S Gopinath, P Nalla, M Thorum, L Schloss, DM Anjos, P Meshram, ... 2015 IEEE International Interconnect Technology Conference and 2015 IEEE …, 2015 | 12 | 2015 |
| Etching substrates using ALE and selective deposition S Tan, J Yu, R Wise, N Shamma, Y Pan US Patent 10,685,836, 2020 | 11 | 2020 |
| Tin oxide films in semiconductor device manufacturing J Yu, SSH Tan, Y Jiang, HJ Wu, R Wise, Y Pan, N Shamma, B Volosskiy US Patent 11,322,351, 2022 | 9 | 2022 |
| Dielectric liner reliability in via-middle through silicon vias with 3 Micron diameter Y Li, S Van Huylenbroeck, P Roussel, M Brouri, S Gopinath, DM Anjos, ... Microelectronic Engineering 156, 37-40, 2016 | 9 | 2016 |
| Development of self-aligned contact technology for 0.18 μm static random access memory devices J Qiao, B Jin, P Phatak, J Yu, S Geha Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 1999 | 8 | 1999 |
Nader ShammaTechnical Director, Lam Research CorpVerified email at lamresearch.com
