Follow
Shailja Pandey
Shailja Pandey
PhD Candidate, IIT Delhi
Verified email at iitd.ac.in - Homepage
Title
Cited by
Cited by
Year
CoMeT: An integrated interval thermal simulation toolchain for 2D, 2.5 D, and 3D processor-memory systems
L Siddhu, R Kedia, S Pandey, M Rapp, A Pathania, J Henkel, PR Panda
ACM Transactions on Architecture and Code Optimization (TACO) 19 (3), 1-25, 2022
172022
NeuroMap: Efficient task mapping of deep neural networks for dynamic thermal management in high-bandwidth memory
S Pandey, PR Panda
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022
82022
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching
S Pandey, L Siddhu, PR Panda
ACM Transactions on Design Automation of Electronic Systems 29 (1), 1-35, 2023
12023
3D-TemPo: Optimizing 3D DRAM Performance Under Temperature and Power Constraints
S Pandey, S Sethi, PR Panda
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024
2024
Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel Closure
L Siddhu, A Bagchi, R Kedia, I Ahmad, S Pandey, PR Panda
ACM Transactions on Embedded Computing Systems 22 (6), 1-27, 2023
2023
Education Abstract: Thermal Challenges and Mitigation in 3D DRAM
PR Panda, S Pandey
Proceedings of the 2023 International Conference on Hardware/Software …, 2023
2023
P4+ BACUS for developing high-performance software switches
A Bhardwaj, S Pandey, A Panda, S Bansal
COP: Compiler Optimizations to Reduce Memory Stalls for Network Pipelines Written in P4
S Pandey, A Bhardwaj, A Panda, S Bansal
The system can't perform the operation now. Try again later.
Articles 1–8