Suivre
Soumya Pandit, M.Sc, M.Tech, Ph.D., MIE(I), SMIEEE
Soumya Pandit, M.Sc, M.Tech, Ph.D., MIE(I), SMIEEE
Assistant Professor, Stage-III, Institute of Radio Physics and Electronics, University of Calcutta
Adresse e-mail validée de caluniv.ac.in - Page d'accueil
Titre
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Année
Nano-scale CMOS analog circuits: models and CAD techniques for high-level design
S Pandit, C Mandal, A Patra
CRC Press, 2018
282018
Insect moulting hormone, ecdysterone, from Sida carpinifolia Linn.
SS Pandit, SD Naik, VS Jathar, AB Kulkarni
171976
Smart health monitoring system for temperature, blood oxygen saturation, and heart rate sensing with embedded processing and transmission using IoT platform
S Basu, S Saha, S Pandit, S Barman
Computational Intelligence in Pattern Recognition: Proceedings of CIPR 2019 …, 2020
152020
Modeling and design of a nano scale cmos inverter for symmetric switching characteristics
J Mukhopadhyay, S Pandit
VLSI Design 2012 (1), 505983, 2012
142012
Systematic methodology for high-level performance modeling of analog systems
S Pandit, C Mandal, A Patra
2009 22nd International Conference on VLSI Design, 361-366, 2009
132009
Effects of BOX engineering on analogue/RF and circuit performance of InGaAs-OI-Si MOSFET
SK Maity, S Pandit
International Journal of Electronics 104 (11), 1777-1794, 2017
102017
Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor
S Sengupta, S Pandit
International Journal of Electronics 102 (6), 967-981, 2015
102015
Channel Profile Design ofDC MOSFET for High Intrinsic Gain and LowMismatch
S Sengupta, S Pandit
IEEE Transactions on Electron Devices 63 (2), 551-557, 2016
92016
Study of GS/D underlap for enhanced analog performance and RF/circuit analysis of UTB InAs-OI-Si MOSFET using NQS small signal model
SK Maity, S Pandit
Superlattices and Microstructures 101, 362-372, 2017
82017
A fast exploration procedure for analog high-level specification translation
S Pandit, SK Bhattacharya, C Mandal, A Patra
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
82008
Study of analog and RF performance of UTB-OI-Si substrate MOS transistor using buffered InGaAs and Silicon channel
SK Maity, S Pandit
2015 6th International conference on computers and devices for communication …, 2015
72015
Adaptive sampling algorithm for ANN-based performance modeling of nano-scale CMOS inverter
D Dhabak, S Pandit
World Acad Sci Eng Technol 80, 812-818, 2011
62011
Design of a Nano-scale CMOS Inverter with Symmetric Switching Characteristics using Particle Swarm Optimization Algorithm
J Mukhopadhyay, S Pandit
IEMCON, 0
6*
Study of temperature variation on threshold voltage and sub-threshold slope of EDC MOS transistor including quantum corrections and reduction techniques
R Das, AK Gond, S Sengupta, RR Sahani, S Pandit
Microsystem Technologies 23 (9), 4221-4229, 2017
52017
Analysis of scaling of thickness of the buffer layer on analog/RF and circuit performance of InAs‐OI‐Si MOSFET using NQS model
SK Maity, S Pandit
International Journal of Numerical Modelling: Electronic Networks, Devices …, 2020
42020
Compact drain current modeling of InAs-OI-Si MOS transistor including quantum confinement
SK Maity, S Pandit
2018 International Symposium on Devices, Circuits and Systems (ISDCS), 1-5, 2018
42018
Nanoscale MOSFET: MOS transistor as basic building block
S Pandit
Introduction to Nano: Basics to Nanoscience and Nanotechnology, 145-172, 2015
42015
A Methodology for Generation of Performance Models for the Sizing of Analog High‐Level Topologies
S Pandit, C Mandal, A Patra
VLSI Design 2011 (1), 475952, 2011
42011
An automated high-level topology generation procedure for continuous-time ΣΔ modulator
S Pandit, C Mandal, A Patra
Integration 43 (3), 289-304, 2010
42010
High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count
S Pandit, S Kar, C Mandal, A Patra
Proceedings of the Design Automation & Test in Europe Conference 1, 1-2, 2006
42006
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