Rodrigo Alvarez-Icaza Rivera
Rodrigo Alvarez-Icaza Rivera
IBM research, Stanford University, University of Pennsylvania
Verified email at us.ibm.com
Title
Cited by
Cited by
Year
A million spiking-neuron integrated circuit with a scalable communication network and interface
PA Merolla, JV Arthur, R Alvarez-Icaza, AS Cassidy, J Sawada, ...
Science 345 (6197), 668-673, 2014
19222014
Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores
A. S. Cassidy, P. Merolla, J. V. Arthur, S. Esser, B. Jackson, R. Alvarez ...
International Joint Conference on Neural Networks (IJCNN), 2013
1091*2013
Neurogrid: A mixed-analog-digital multichip system for large-scale neural simulations
BV Benjamin, P Gao, E McQuinn, S Choudhary, AR Chandrasekaran, ...
Proceedings of the IEEE 102 (5), 699-716, 2014
6682014
Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip
F Akopyan, J Sawada, A Cassidy, R Alvarez-Icaza, J Arthur, P Merolla, ...
IEEE transactions on computer-aided design of integrated circuits and …, 2015
4912015
Building block of a programmable neuromorphic substrate: A digital neurosynaptic core
JV Arthur, PA Merolla, F Akopyan, R Alvarez, A Cassidy, S Chandra, ...
the 2012 international joint conference on Neural networks (IJCNN), 1-8, 2012
1592012
A million spiking-neuron integrated circuit with a scalable communication network and interface
AM Paul, JV Arthur, R Alvarez-Icaza, AS Cassidy, J Sawada, F Akopyan, ...
Science 345 (6197), 668-673, 2014
1582014
Cognitive computing systems: Algorithms and applications for networks of neurosynaptic cores
SK Esser, A Andreopoulos, R Appuswamy, P Datta, D Barch, A Amir, ...
The 2013 International Joint Conference on Neural Networks (IJCNN), 1-10, 2013
1552013
Cognitive computing programming paradigm: a corelet language for composing networks of neurosynaptic cores
A Amir, P Datta, WP Risk, AS Cassidy, JA Kusnitz, SK Esser, ...
The 2013 International Joint Conference on Neural Networks (IJCNN), 1-10, 2013
1372013
Real-time scalable cortical computing at 46 giga-synaptic OPS/watt with~ 100× speedup in time-to-solution and~ 100,000× reduction in energy-to-solution
AS Cassidy, R Alvarez-Icaza, F Akopyan, J Sawada, JV Arthur, ...
SC'14: Proceedings of the International Conference for High Performance …, 2014
702014
A multicast tree router for multichip neuromorphic systems
P Merolla, J Arthur, R Alvarez, JM Bussat, K Boahen
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (3), 820-833, 2013
502013
Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications
J Sawada, F Akopyan, AS Cassidy, B Taba, MV Debole, P Datta, ...
SC'16: Proceedings of the International Conference for High Performance …, 2016
492016
Showcasing of products featured in entertainment productions
A Marshall
US Patent App. 10/410,109, 2004
362004
Consolidating multiple neurosynaptic cores into one memory
RAI Rivera, JV Arthur, AS Cassidy, PA Merolla, DS Modha
US Patent 8,990,130, 2015
352015
Dielectric elastomer fiber transducers
RAI Rivera, JMA Sanches, KC Galloway, HS Katzenberg, R Kothari, ...
US Patent 7,834,527, 2010
262010
Multiplexing physical neurons to optimize power and area
RAI Rivera, JV Arthur, AS Cassidy, PA Merolla, DS Modha
US Patent 9,159,020, 2015
242015
Visual saliency on networks of neurosynaptic cores
A Andreopoulos, B Taba, AS Cassidy, R Alvarez-Icaza, MD Flickner, ...
IBM Journal of Research and Development 59 (2/3), 9: 1-9: 16, 2015
222015
Spiking optical flow for event-based sensors using IBM's truenorth neurosynaptic system
G Haessig, A Cassidy, R Alvarez, R Benosman, G Orchard
IEEE transactions on biomedical circuits and systems 12 (4), 860-870, 2018
192018
Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation
RAI Rivera, R Appuswamy, JV Arthur, AS Cassidy, BL Jackson, ...
US Patent 10,650,301, 2020
132020
Faulty core recovery mechanisms for a three-dimensional network on a processor array
RAI Rivera, JV Arthur, JE Barth Jr, AS Cassidy, S Iyer, PA Merolla, ...
US Patent 9,160,617, 2015
132015
Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits
FA Akopyan, RAI Rivera, JV Arthur, AS Cassidy, BL Jackson, PA Merolla, ...
US Patent 9,852,006, 2017
122017
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