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Hemangee K Kapoor
Hemangee K Kapoor
Verified email at iitg.ernet.in
Title
Cited by
Cited by
Year
A security framework for noc using authenticated encryption and session keys
HK Kapoor, GB Rao, S Arshi, G Trivedi
Circuits, Systems, and Signal Processing 32, 2605-2622, 2013
602013
An authenticated encryption based security framework for NoC architectures
K Sajeesh, HK Kapoor
2011 International Symposium on Electronic System Design, 134-139, 2011
402011
Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines
D Deb, J Jose, S Das, HK Kapoor
Journal of Parallel and Distributed Computing 123, 118-129, 2019
292019
Energy aware frame based fair scheduling
S Moulik, A Sarkar, HK Kapoor
Sustainable Computing: Informatics and Systems 18, 66-77, 2018
222018
Analysing the role of last level caches in controlling chip temperature
S Chakraborty, HK Kapoor
IEEE Transactions on Sustainable Computing 3 (4), 289-305, 2018
202018
Towards near data processing of convolutional neural networks
P Das, S Lakhotia, P Shetty, HK Kapoor
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
172018
Victim retention for reducing cache misses in tiled chip multiprocessors
S Das, HK Kapoor
Microprocessors and Microsystems 38 (4), 263-275, 2014
172014
TARTS: A temperature-aware real-time deadline-partitioned fair scheduler
S Moulik, A Sarkar, HK Kapoor
Journal of Systems Architecture 112, 101847, 2021
162021
Improving the lifetime of non-volatile cache by write restriction
S Agarwal, HK Kapoor
IEEE Transactions on Computers 68 (9), 1297-1312, 2019
162019
Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench
HK Kapoor, MB Josephs
Information Processing Letters 89 (6), 293-296, 2004
162004
Reuse-distance-aware write-intensity prediction of dataless entries for energy-efficient hybrid caches
S Agarwal, HK Kapoor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (10 …, 2018
152018
Dpfair scheduling with slowdown and suspension
S Moulik, A Sarkar, HK Kapoor
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
152018
Restricting writes for energy-efficient hybrid cache in multi-core architectures
S Agarwal, HK Kapoor
2016 IFIP/IEEE International Conference on Very Large Scale Integration …, 2016
152016
Exploration of migration and replacement policies for dynamic NUCA over tiled CMPs
S Das, HK Kapoor
2015 28th International Conference on VLSI Design, 141-146, 2015
152015
Fault tolerance in network on chip using bypass path establishing packets
S Priya, S Agarwal, HK Kapoor
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
142018
Exploring the role of large centralised caches in thermal efficient chip design
S Chakraborty, HK Kapoor
ACM Transactions on Design Automation of Electronic Systems (TODAES) 24 (5 …, 2019
132019
Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets
S Agarwal, HK Kapoor
2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017
132017
Static energy reduction by performance linked cache capacity management in tiled cmps
HK Kapoor, S Das, S Chakraborty
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 1913-1918, 2015
122015
Dynamic Associativity Management using Fellow Sets
S Das, HK Kapoor
International Symposium on Electronic System Design (ISED), 2013
122013
Formal approach for DVS-based power management for multiple server system in presence of server failure and repair
L Chandnani, HK Kapoor
IEEE Transactions on Industrial Informatics 9 (1), 502-513, 2012
122012
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