Debjyoti Bhattacharjee
Title
Cited by
Cited by
Year
ReVAMP: ReRAM based VLIW architecture for in-memory computing
D Bhattacharjee, R Devadoss, A Chattopadhyay
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
422017
Depth-optimal quantum circuit placement for arbitrary topologies
D Bhattacharjee, A Chattopadhyay
arXiv preprint arXiv:1703.08540, 2017
182017
Delay-optimal technology mapping for in-memory computing using ReRAM devices
D Bhattacharjee, A Chattopadhyay
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2016
162016
Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays
D Bhattacharjee, F Merchant, A Chattopadhyay
2016 IFIP/IEEE International Conference on Very Large Scale Integration …, 2016
122016
Multi-valued and fuzzy logic realization using TaOx memristive devices
D Bhattacharjee, W Kim, A Chattopadhyay, R Waser, V Rana
Scientific reports 8 (1), 1-10, 2018
112018
Efficient binary basic linear algebra operations on reram crossbar arrays
D Bhattacharjee, A Chattopadhyay
2017 30th international conference on VLSI design and 2017 16th …, 2017
92017
Technology-aware logic synthesis for ReRAM based in-memory computing
D Bhattacharjee, L Amaŕu, A Chattopadhyay
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
82018
Efficient complementary resistive switch-based crossbar array booth multiplier
D Bhattacharjee, A Siemon, E Linn, A Chattopadhyay
Microelectronics Journal 64, 78-85, 2017
82017
Area-constrained technology mapping for in-memory computing using reram devices
D Bhattacharjee, A Easwaran, A Chattopadhyay
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 69-74, 2017
72017
Efficient hardware accelerator for AEGIS-128 authenticated encryption
D Bhattacharjee, A Chattopadhyay
International Conference on Information Security and Cryptology, 385-402, 2014
72014
SHA-3 implementation using ReRAM based in-memory computing architecture
D Bhattacharjee, V Pudi, A Chattopadhyay
2017 18th International Symposium on Quality Electronic Design (ISQED), 325-330, 2017
62017
Ensemble Classifier based approach for Code-Mixed Cross-Script Question Classification
D Bhattacharjee, P Bhattacharya
Working notes of {FIRE} 2016 - Forum for Information Retrieval Evaluation …, 2016
6*2016
Evodeb: Debugging evolving hardware designs
D Bhattacharjee, A Banerjee, A Chattopadhyay
2015 28th International Conference on VLSI Design, 481-486, 2015
52015
Techniques for fault-tolerant decomposition of a multicontrolled Toffoli gate
L Biswal, D Bhattacharjee, A Chattopadhyay, H Rahaman
Physical Review A 100 (6), 062326, 2019
42019
Sklansky tree adder realization in 1S1R resistive switching memory architecture
A Siemon, S Menzel, D Bhattacharjee, R Waser, A Chattopadhyay, E Linn
The European Physical Journal Special Topics 228 (10), 2269-2285, 2019
42019
SIMPLER MAGIC: synthesis and mapping of in-memory logic executed in a single row to improve throughput
R Ben-Hur, R Ronen, A Haj-Ali, D Bhattacharjee, A Eliahu, N Peled, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019
42019
SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars
V Tenace, RG Rizzo, D Bhattacharjee, A Chattopadhyay, A Calimera
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 372-377, 2019
42019
Synthesis of multi-valued literal using Lukasiewicz logic
AP Surhonne, D Bhattacharjee, A Chattopadhyay
2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), 204-209, 2018
42018
Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays
D Bhattacharjee, A Siemon, E Linn, S Menzel, A Chattopadhyay
ACM Journal on Emerging Technologies in Computing Systems (JETC) 14 (2), 1-14, 2018
32018
In-memory data compression using ReRAMs
D Bhattacharjee, A Chattopadhyay
Emerging Technology and Architecture for Big-data Analytics, 275-291, 2017
32017
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Articles 1–20