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Anup Dandapat
Anup Dandapat
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Title
Cited by
Cited by
Year
Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit
P Bhattacharyya, B Kundu, S Ghosh, V Kumar, A Dandapat
IEEE Transactions on very large scale integration (VLSI) systems 23 (10…, 2014
2872014
High speed ASIC design of complex multiplier using vedic mathematics
P Saha, A Banerjee, P Bhattacharyya, A Dandapat
IEEE Technology Students' Symposium, 237-241, 2011
1332011
A 1.2-ns16 16-bit binary multiplier using high speed compressors
A Dandapat, S Ghosal, P Sarkar, D Mukhopadhyay
International Journal of Electrical and Electronics Engineering 4 (3), 234-239, 2010
792010
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics
P Saha, A Banerjee, A Dandapat, P Bhattacharyya
Microelectronics journal 42 (12), 1343-1352, 2011
442011
Self-controlled high-performance precharge-free content-addressable memory
TV Mahendra, S Mishra, A Dandapat
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8…, 2017
372017
Improved matrix multiplier design for high‐speed digital signal processing applications
P Saha, A Banerjee, P Bhattacharyya, A Dandapat
IET circuits, devices & systems 8 (1), 27-37, 2014
262014
A 9-T 833-MHz 1.72-fJ/bit/search quasi-static ternary fully associative cache tag with selective matchline evaluation for wire speed applications
S Mishra, TV Mahendra, A Dandapat
IEEE Transactions on Circuits and Systems I: Regular Papers 63 (11), 1910-1920, 2016
242016
High speed low power complex multiplier design using parallel adders and subtractors
PK Saha, A Banerjee, A Dandapat
International Journal on Electronic and Electrical Engineering,(IJEEE) 7 (11…, 2009
242009
Design of high performance 8 bit multiplier using vedic multiplication algorithm with McCMOS technique
D Kayal, P Mostafa, A Dandapat, CK Sarkar
Journal of Signal Processing Systems 76 (1), 1-9, 2014
232014
Vedic divider: Novel architecture (ASIC) for high speed VLSI applications
P Saha, A Banerjee, P Bhattacharyya, A Dandapat
2011 International Symposium on Electronic System Design, 67-71, 2011
192011
Ultra low-power sequential circuit implementation by a Quasi-Static Single phase Adiabatic Dynamic Logic (SPADL)
M Chanda, A Dandapat, H Rahaman
TENCON 2009-2009 IEEE Region 10 Conference, 1-5, 2009
192009
Match-line division and control to reduce power dissipation in content addressable memory
SW Hussain, TV Mahendra, S Mishra, A Dandapat
IEEE Transactions on Consumer Electronics 64 (3), 301-309, 2018
172018
Vedic mathematics based 32-bit multiplier design for high speed low power processors
P Saha, A Banerjee, A Dandapat, P Bhattacharyya
International journal on smart sensing and Intelligent Systems 4 (2), 2011
162011
Design of high speed vedic multiplier for decimal number system
P Saha, A Banerjee, A Dandapat, P Bhattacharyya
Progress in VLSI Design and Test, 79-88, 2012
152012
Hardware implementation of methodologies of fixed point division algorithms
D Kumar, P Saha, A Dandapat
International Journal on Smart Sensing and Intelligent Systems 10 (3), 1-16, 2017
122017
Vedic algorithm for cubic computation and VLSI implementation
D Kumar, P Saha, A Dandapat
Engineering science and technology, an international journal 20 (5), 1494-1499, 2017
112017
ASIC implementation of high speed processor for calculating discrete fourier transformation using circular convolution technique
P Saha, A Banerjee, A Dandapat, P Bhattacharyya
WSEAS Transactions on Circuits and Systems 10 (8), 278-288, 2011
112011
Precharge free dynamic content addressable memory
TV Mahendra, SW Hussain, S Mishra, A Dandapat
Electronics Letters 54 (9), 556-558, 2018
102018
A low-overhead dynamic TCAM with pipelined read-restore refresh scheme
S Mishra, TV Mahendra, J Saikia, A Dandapat
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (5), 1591-1601, 2017
102017
Vedic division methodology for high‐speed very large scale integration applications
P Saha, D Kumar, P Bhattacharyya, A Dandapat
The Journal of Engineering 2014 (2), 51-59, 2014
102014
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