D.Gracia Nirmala Rani
D.Gracia Nirmala Rani
Assistant Professor, Department of ECE, Thiagarajar College of Engineering, Madurai, India.
Verified email at tce.edu - Homepage
Cited by
Cited by
Vlsi floorplanning relying on differential evolution algorithm
DJ Moni, S Arumugam, GN Rani
ICGST International Journal on Artificial Intelligence and Machine Learning …, 2007
Thermal aware modern VLSI floorplanning
NRD Gracia, S Rajaram, A Sudarsan
2012 International Conference on Devices, Circuits and Systems (ICDCS), 187-190, 2012
Design and optimisation of feedforward noise cancelling complementary metal oxide semiconductor LNA for 2.4 GHz WLAN applications
AA Roobert, DGN Rani, S Rajaram
IET Circuits, Devices & Systems 13 (6), 908-919, 2019
Design of CMOS based LNA for 5G Wireless Applications
AA Roobert, DGN Rani, M Divya, S Rajaram
Proceedings of the 6th International Conference on Communications and …, 2018
A survey on B*–Tree–based evolutionary algorithms for VLSI floorplanning optimisation
DGN Rani, S Rajaram
International journal of computer applications in technology 48 (4), 281-287, 2013
Design and analysis of 0.9 and 2.3‐GHz concurrent dual‐band CMOS LNA for mobile communication
AA Roobert, DGN Rani
International Journal of Circuit Theory and Applications 48 (1), 1-14, 2020
Low hardware overhead implementation of 3-weight pattern generation technique for VLSI testing
DGN Rani, MGM Meenakshi, SA Marina
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS), 1-5, 2014
Performance Driven VLSI Floorplanning with B* Tree Representation Using Differential Evolutionary Algorithm
DGN Rani, S Rajaram
Trends in Network and Communications, 445-456, 2011
Survey on parameter optimization of mobile communication band low noise amplifier design
AA Roobert, DGN Rani
International Journal of RF and Microwave Computer‐Aided Engineering 29 (7 …, 2019
A novel 3D algorithm for VLSI floorplanning
DGN Rani, S Rajaram, A Sudarasan
International Conference on Communication and Electronics System Design 8760 …, 2013
Design of CMOS Based Biosensor for Implantable Medical Devices
G Gifta, DGN Rani, N Farhana, R Archana
International Symposium on VLSI Design and Test, 695-704, 2018
Low power VLSI architecture design of BMC, BPSC and PC schemes
DGNR G. Rajakumar, A. Andrew Roobert, T. S. Arun Samuel
Analog Integr Circ Sig Process Springer 93 (1), 169-178, 2017
Design of static random access memory using QCA technology
DGN Rani, M Saranya, T Sivashankari, N Meenakshi, R Meena, ...
2016 3rd International Conference on Devices, Circuits and Systems (ICDCS …, 2016
A novel differential evolution based optimization algorithm for Non-Sliceable VLSI floorplanning
D Gracia Nirmala Rani, S Rajaram
Iranian Journal of Science and Technology (Sciences) 39 (3.1), 375-382, 2015
Design and analysis of a sleep and wake-up CMOS low noise amplifier for 5G applications
AA Roobert, DGN Rani
Telecommunication Systems, 1-10, 2020
A 1-V, 5 μW, Atto Current Bulk-Driven CMOS Based Operational Transconductance Amplifier for Biosensor Applications
G Gifta, DGN Rani, D Nirmal
ECS Journal of Solid State Science and Technology 9 (11), 115003, 2020
Design and Analysis of CMOS Low Power OTA for Biomedical Applications
DGN Rani, G Gifta, M Meenakshi, C Gomathy, T Gowsalaya
2019 4th International Conference on Recent Trends on Electronics …, 2019
VLSI Design and Test: 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers
S Rajaram, NB Balamurugan, DGN Rani, V Singh
Springer, 2019
3D-IC Partitioning and TSV Sharing Optimization Algorithm
M Sarojini, DGN Rani
Journal of Multimedia Technology & Recent Advancements 3 (2), 6-10, 2016
Design and implementation of Configurable Logic Block of an FPGA using quantum dot cellular automata
DGN Rani, C Mathumitha, R Priyadharshini, S Rajaram
2016 3rd International Conference on Devices, Circuits and Systems (ICDCS …, 2016
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