Gurshaant Singh Malik
Gurshaant Singh Malik
Machine Learning Scientist 3, Applied Brain Research Inc.
Verified email at - Homepage
Cited by
Cited by
System and method for a database proxy
C Kulkarni, A Alurkar, P Mishra, P Sukumar, V Raghava, R Raj, ...
US Patent 10,237,350, 2019
FPGA based hierarchical architecture for parallelizing RRT
GS Malik, K Gupta, KM Krishna, SR Chowdhury
Proceedings of the 2015 Conference on Advances In Robotics, 1-6, 2015
Hardware Aware Training for Efficient Keyword Spotting on General Purpose and Specialized Hardware
P Blouw, G Malik, B Morcos, AR Voelker, C Eliasmith
arXiv preprint arXiv:2009.04465, 2020
Enhancing butterfly fat tree nocs for fpgas with lightweight flow control
GS Malik, N Kapre
2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019
FPGA based massively parallel architectures for super fast path planning via Rapidly Exploring Random Trees (RRT)
GS Malik
MA thesis. International Institute of Information Technology, Hyderabad …, 2016
FPGA based hybrid architecture for parallelizing RRT
G Malik, K Gupta, R Dharani, KM Krishna
arXiv preprint arXiv:1607.05704, 2016
K-Means derived strategized placement of starting points for parallel RRT’s
KM Krishna
Proc. IIIT Hyderabad, 145, 2016
FPGA based combinatorial architecture for parallelizing RRT
GS Malik, K Gupta, KM Krishna, SR Chowdhury
2015 European Conference on Mobile Robots (ECMR), 1-6, 2015
Decision theoretic search for small objects through integrating far and near cues
MS Karthik, S Mittal, G Malik, KM Krishna
2015 European Conference on Mobile Robots (ECMR), 1-6, 2015
Learn the Switches: Evolving FPGA NoCs with Stall-Free and Backpressure Based Routers
G Malik, IE Lang, R Pellizoni, N Kapre
2020 30th International Conference on Field-Programmable Logic and …, 2020
DarwiNN: efficient distributed neuroevolution under communication constraints
GS Malik, L Petrica, N Kapre, M Blott
Proceedings of the 2020 Genetic and Evolutionary Computation Conference …, 2020
Partitioning FPGA-Optimized Systolic Arrays for Fun and Profit
LC Chan, G Malik, N Kapre
2019 International Conference on Field-Programmable Technology (ICFPT), 144-152, 2019
FPGA Based Massively Parallel Hybrid Architecture for Parallelizing RRTs
GS Malik, K Gupta, R Dharani, KM Krishna
International Journal of Mechanical Engineering and Robotics Research 6 (6), 2017
FPL 2020
G Malik, IE Lang, E Karabulut, A Aysu
K-Means derived software defined multi-RRT seeding for FPGA based super-parallel implementation via Hierarchical architecture
K Gupta, GS Malik, KM Krishna
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