| A novel BIST TPG for testing of VLSI circuits K Gunavathi, K Paramasivam, PS Lavanya, M Umamageswaran First International Conference on Industrial and Information Systems, 109-114, 2006 | 42 | 2006 |
| An optimised 3D topology for on-chip communications N Viswanathan, K Paramasivam, K Somasundaram International Journal of Parallel, Emergent and Distributed Systems 29 (4 …, 2014 | 15 | 2014 |
| Hybrid Adaptive Call Admission Control Mechanism for Ensuring QoS in 3GPP: LTE Networks JV Franklin, K Paramasivam International Journal of Computer Applications 42 (21), 36-41, 2012 | 14 | 2012 |
| Efficient Channel State Based Call Admission Control for Non Real Time traffic in LTE (3GPP) Networks JV Franklin, K Paramasivam International Journal of Computer Science 9, 0 | 14* | |
| Reordering Algorithm for Minimizing Test Power in VLSI Circuits. K Paramasivam, K Gunavathi Engineering letters 14 (1), 2007 | 13 | 2007 |
| Design and analysis of low power hybrid memristor-CMOS based distinct binary logic nonvolatile SRAM cell V Saminathan, K Paramasivam Circuits and Systems 7 (3), 119-127, 2016 | 12 | 2016 |
| Exploring Optimal Topology and Routing Algorithm for 3D Network on Chip N Viswanathan, K Paramasivam, K Somasundaram American Journal of Applied Sciences 9, 0 | 12* | |
| Simulation of VLSI design using parallel architecture for epilepsy risk level diagnosis in diabetic neuropathy K Paramasivam, R Harikumar, R Sundararajan IETE journal of research 50 (4), 297-304, 2004 | 11 | 2004 |
| Network on-chip and its research challenges K Paramasivam ICTACT Journal on Microelectronnics 1 (02), 2015 | 10 | 2015 |
| Exploring hierarchical, cluster based 3D topologies for 3D NoC N Viswanathan, K Paramasivam, K Somasundaram Procedia Engineering 30, 606-615, 2012 | 9 | 2012 |
| Performance analysis of cluster based 3D routing algorithms for NoC N Viswanathan, K Paramasivam, K Somasundaram 2011 IEEE Recent Advances in Intelligent Computational Systems, 157-162, 2011 | 9 | 2011 |
| Enhanced authentication protocol for improving security in 3GPP LTE networks JV Franklin, K Paramasivam Proc. International Conference on Information and Network Technology (ICINT …, 2011 | 9 | 2011 |
| Utility based scheduling and call admission control for LTE (3GPP) networks J Vijay Franklin, K Paramasivam J Inform Tech Softw Eng 2 (113), 2, 2012 | 8 | 2012 |
| A comprehensive study on the characteristics, complex materials and applications of memristor N Nithya, K Paramasivam 2020 6th International Conference on Advanced Computing and Communication …, 2020 | 7 | 2020 |
| Switching activity based method for minimizing testing power in digital circuits K Paramasivam, K Gunavathi ECTI Transactions on Electrical Engineering, Electronics, and Communications …, 2007 | 7 | 2007 |
| A Novel Hybrid CMOS-Memristor Based 2-Bit Magnitude Comparator using Memristor Ratioed Logic Universal Gate for Low Power Applications K Paramasivam, N Nithya, A Nepolean 2021 International Conference on Advancements in Electrical, Electronics …, 2021 | 6 | 2021 |
| Test power minimization of VLSI circuits: A survey GS Kumar, K Paramasivam 2013 Fourth International Conference on Computing, Communications and …, 2013 | 5 | 2013 |
| Modified scan architecture for an effective scan testing K Paramasivam, K Gunavathi, A Nirmalkumar TENCON 2008-2008 IEEE Region 10 Conference, 1-6, 2008 | 5 | 2008 |
| Algorithm for low power combinational circuit testing K Paramasivam, K Gunavathi, P Sathishkumar 2004 IEEE Region 10 Conference TENCON 2004. 500, 336-339, 2004 | 5 | 2004 |
| Missing Fourth Element Memristor Modeling with New Window Function Derived from Sigmoid Logistic Equation V Saminathan, P Dr,K International Journal of Advanced Engineering Technology 7 (I), 384-386, 2016 | 4 | 2016 |
Dr Vijay FranklinProfessor of computer science,BITVerified email at bitsathy.ac.in
