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Kishor Sarawadekar
Kishor Sarawadekar
Verified email at iitbhu.ac.in - Homepage
Title
Cited by
Cited by
Year
An efficient pass-parallel architecture for embedded block coder in JPEG 2000
K Sarawadekar, S Banerjee
IEEE Transactions on Circuits and Systems for Video Technology 21 (6), 825-836, 2011
332011
Polynomial learning rate policy with warm restart for deep neural network
P Mishra, K Sarawadekar
TENCON 2019-2019 IEEE Region 10 Conference (TENCON), 2087-2092, 2019
282019
Towards hand gesture based writing support system for blinds
G Modanwal, K Sarawadekar
Pattern Recognition 57, 50-60, 2016
272016
An optimized architecture of HEVC core transform using real-valued DCT coefficients
S Chatterjee, K Sarawadekar
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (12), 2052-2056, 2018
192018
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000
K Sarawadekar, S Banerjee
Integration 45 (1), 1-8, 2012
162012
A robust wrist point detection algorithm using geometric features
G Modanwal, K Sarawadekar
Pattern Recognition Letters 110, 72-78, 2018
152018
A new dactylology and interactive system development for blind–computer interaction
G Modanwal, K Sarawadekar
IEEE Transactions on Human-Machine Systems 48 (2), 207-212, 2017
132017
Low-cost, high-performance VLSI design of an MQ coder for JPEG 2000
K Sarawadekar, S Banerjee
IEEE 10th INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING PROCEEDINGS, 397-400, 2010
112010
Development of a new dactylology and writing support system especially for blinds
G Modanwal, K Sarawadekar
2016 13th Conference on Computer and Robot Vision (CRV), 362-369, 2016
102016
A gesture elicitation study with visually impaired users
G Modanwal, K Sarawadekar
International Conference on Human-Computer Interaction, 54-61, 2018
82018
WHT and matrix decomposition-based approximated IDCT architecture for HEVC
S Chatterjee, K Sarawadekar
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (6), 1043-1047, 2018
72018
An FPGA-based architecture of DSC–SRI units specially for motion blind ultrasound systems
R Biswas, K Sarawadekar, S Varna, S Banerjee
Journal of Real-Time Image Processing 10 (3), 573-595, 2015
72015
Area efficient, high-speed VLSI design for EBCOT block coder in JPEG 2000
K Sarawadekar, S Banerjee
2010 International Conference on Electronics and Information Engineering 2 …, 2010
72010
Gender recognition using in-built inertial sensors of smartphone
T Meena, K Sarawadekar
2020 IEEE REGION 10 CONFERENCE (TENCON), 462-467, 2020
62020
Fingertips detection in egocentric video frames using deep neural networks
P Mishra, K Sarawadekar
2019 International Conference on Image and Vision Computing New Zealand …, 2019
62019
A decentralized beam selection for mmWave beamspace multi-user MIMO system
R Pal, KP Sarawadekar, KV Srinivas
AEU-International Journal of Electronics and Communications 111, 152884, 2019
62019
VLSI-DSP based real time solution of DSC–SRI for an ultrasound system
KP Sarawadekar, HB Indana, D Bera, S Banerjee
Microprocessors and Microsystems 36 (1), 1-12, 2012
62012
Efficient VLSI architecture for bit plane encoder of JPEG 2000
K Sarawadekar, S Banerjee
2009 16th IEEE International Conference on Image Processing (ICIP), 2805-2808, 2009
62009
A high speed bit plane coder for JPEG 2000 and it's FPGA implementation
K Sarawadekar, S Banerjee
2009 17th European Signal Processing Conference, 2231-2234, 2009
62009
VLSI implementation of MQ decoder in JPEG2000
OC Kulkarni, K Sarawadekar, S Banerjee
IEEE Technology Students' Symposium, 193-197, 2011
52011
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