Seznec Andre
Seznec Andre
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A case for two-way skewed-associative caches
A Seznec
ACM SIGARCH computer architecture news 21 (2), 169-178, 1993
A case for (partially) tagged geometric history length branch prediction
A Seznec, P Michaud
The Journal of Instruction-Level Parallelism 8, 23, 2006
Design tradeoffs for the Alpha EV8 conditional branch predictor
A Seznec, S Felix, V Krishnan, Y Sazeides
ACM SIGARCH Computer Architecture News 30 (2), 295-306, 2002
Trading conflict and capacity aliasing in conditional branch predictors
P Michaud, A Seznec, R Uhlig
Proceedings of the 24th annual international symposium on Computerá…, 1997
A 256 kbits l-tage branch predictor
A Seznec
Journal of Instruction-Level Parallelism (JILP) Special Issue: The Secondá…, 2007
Analysis of the o-geometric history length branch predictor
A Seznec
32nd International Symposium on Computer Architecture (ISCA'05), 394-405, 2005
Decoupled sectored caches: conciliating low tag implementation cost
A Seznec
Proceedings of the 21st annual international symposium on Computerá…, 1994
Zero-content augmented caches
J Dusser, T Piquet, A Seznec
Proceedings of the 23rd international conference on Supercomputing, 46-55, 2009
Performance implications of single thread migration on a chip multi-core
T Constantinou, Y Sazeides, P Michaud, D Fetis, A Seznec
ACM SIGARCH Computer Architecture News 33 (4), 80-91, 2005
Multiple-block ahead branch predictors
A Seznec, S Jourdan, P Sainrat, P Michaud
ACM SIGPLAN Notices 31 (9), 116-127, 1996
A new case for the tage branch predictor
A Seznec
Proceedings of the 44th Annual IEEE/ACM International Symposium oná…, 2011
Improving cache behavior of dynamically allocated data structures
DN Truong, F Bodin, A Seznec
Proceedings. 1998 International Conference on Parallel Architectures andá…, 1998
Tarantula: a vector extension to the alpha architecture
R Espasa, F Ardanaz, J Emer, S Felix, J Gago, R Gramunt, I Hernandez, ...
ACM SIGARCH Computer Architecture News 30 (2), 281-292, 2002
Choosing representative slices of program execution for microarchitecture simulations: A preliminary application to the data stream
T Lafage, A Seznec
Workload characterization of emerging computer applications, 145-163, 2001
Data-flow prescheduling for large instruction windows in out-of-order processors
P Michaud, A Seznec
Proceedings HPCA Seventh International Symposium on High-Performanceá…, 2001
The strict avalanche criterion randomness test
JCH Castro, JM Sierra, A Seznec, A Izquierdo, A Ribagorda
Mathematics and Computers in Simulation 68 (1), 1-7, 2005
Performance upper bound analysis and optimization of SGEMM on Fermi and Kepler GPUs
J Lai, A Seznec
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generationá…, 2013
Practical and secure pcm systems by online detection of malicious write streams
MK Qureshi, A Seznec, LA Lastras, MM Franceschini
2011 IEEE 17th International symposium on high performance computerá…, 2011
Skewed-associative caches
A Seznec, F Bodin
PARLE'93 Parallel Architectures and Languages Europe: 5th Internationalá…, 1993
Prediction-based superpage-friendly TLB designs
MM Papadopoulou, X Tong, A Seznec, A Moshovos
2015 IEEE 21st International Symposium on High Performance Computerá…, 2015
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