Dr. Ajay Kumar Dadoria
Dr. Ajay Kumar Dadoria
MANIT, Bhopal
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Cited by
Cited by
Year
Ultra-low power FinFET-based domino circuits
AK Dadoria, K Khare, TK Gupta, RP Singh
International Journal of Electronics 104 (6), 952-967, 2017
142017
A novel approach for leakage power reduction techniques in 65nm technologies
AK Dadoria, K Khare
International Journal of VLSI design & Communication Systems 5 (3), 1, 2014
112014
Comparative analysis of variable NT sram cells
AK Dadoria, AS Yadav, CM Roy
International Journal of Advanced Research in Computer Science and Software …, 2013
112013
Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits
AK Dadoria, K Khare, TK Gupta, N Khare
Journal of Computational Electronics 16 (3), 867-874, 2017
92017
A novel approach for leakage power reduction in deep submicron technologies in CMOS VLSI circuits
AK Dadoria, K Khare, RP Singh
2015 International Conference on Computer, Communication and Control (IC4), 1-6, 2015
92015
A Novel High-Performance Lekage-Tolerant, Wide Fan-In Domino Logic Circuit in Deep-Submicron Technology
A Dadoria, K Khare, TK Gupta, RP Singh
Circuits and Systems 6 (04), 103, 2015
92015
Leakage reduction by using FinFET technique for nanoscale technology circuits
AK Dadoria, K Khare, TK Gupta, RP Singh
Journal of Nanoelectronics and Optoelectronics 12 (3), 278-285, 2017
62017
Ultra low power adiabatic logic using diode connected DC biased PFAL logic
A Agrawal, TK Gupta, AK Dadoria
Advances in Electrical and Electronic Engineering 15 (1), 46-54, 2017
52017
A novel efficient adiabatic logic design for ultra low power
A Agrawal, TK Gupta, AK Dadoria, D Kumar
2016 International Conference on ICT in Business Industry & Government …, 2016
52016
Sleepy lector: A novel approach for leakage reduction in DSM technology
AK Dadoria, K Khare, RP Singh
2016 6th International Conference-Cloud System and Big Data Engineering …, 2016
52016
A New CMOS Voltage Divider Based Current Mirror Compared with the Basic and Cascode Current Mirrors
AK Dadoria, AS Yadav, CM Roy
International Journal of Advanced Research in Computer Science and Software …, 2013
52013
Performance evaluation of domino logic circuits for wide fan-in gates with FinFET
AK Dadoria, K Khare, U Panwar, A Jain
Microsystem Technologies 24 (8), 3341-3348, 2018
42018
Comparative analysis of various Domino logic circuits for better performance
R Thakur, AK Dadoria, TK Gupta
2014 International Conference on Advances in Electronics Computers and …, 2014
42014
Ultra low power high speed domino logic circuit by using FiNFET technology
AK Dadoria, K Khare, TK Gupta, RP Singh
Vysoká škola báňská-Technická univerzita Ostrava, 2016
32016
Leakage Power Reduction Technique by using FinFET Technology
AK Dadoria, K Khare, RP Singh
Proceedings of the Second International Conference on Information and …, 2016
22016
Leakage power reduction technique by using FinFET technology in ulsi circuit design
AK Dadoria, K Khare, TK Gupta, RP Singh
Proceedings of First International Conference on Information and …, 2016
22016
Comparision on Different Domino Logic Design for High-Performance and Leakage-Tolerant Wide OR Gate
U Panwar, AK Dadoria
ISSN, 0
2
New leakage reduction techniques for FinFET technology with its application
AK Dadoria, K Khare, TK Gupta, RP Singh
Journal of Circuits, Systems and Computers 27 (07), 1850112, 2018
12018
Low-Power High Speed 1-bit Full Adder Circuit Design
S Dwivedi, K Khare, AK Dadoria
Proceedings of the Second International Conference on Information and …, 2016
12016
Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology
AK Dadoria, K Khare
Circuits, Systems, and Signal Processing 38 (9), 4338-4356, 2019
2019
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Articles 1–20