| Ultra-low power FinFET-based domino circuits AK Dadoria, K Khare, TK Gupta, RP Singh International Journal of Electronics 104 (6), 952-967, 2017 | 25 | 2017 |
| Ultra low power adiabatic logic using diode connected DC biased PFAL logic A Agrawal, TK Gupta, AK Dadoria Advances in Electrical and Electronic Engineering 15 (1), 46-54, 2017 | 16 | 2017 |
| A novel high-performance lekage-tolerant, wide fan-in domino logic circuit in deep-submicron technology A Dadoria, K Khare, TK Gupta, RP Singh Circuits and Systems 6 (04), 103, 2015 | 15 | 2015 |
| Performance evaluation of domino logic circuits for wide fan-in gates with FinFET AK Dadoria, K Khare, U Panwar, A Jain Microsystem Technologies 24, 3341-3348, 2018 | 14 | 2018 |
| Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits AK Dadoria, K Khare, TK Gupta, N Khare Journal of Computational Electronics 16, 867-874, 2017 | 14 | 2017 |
| A novel approach for leakage power reduction in deep submicron technologies in CMOS VLSI circuits AK Dadoria, K Khare, RP Singh 2015 International Conference on Computer, Communication and Control (IC4), 1-6, 2015 | 13 | 2015 |
| A novel approach for leakage power reduction techniques in 65nm technologies AK Dadoria, K Khare International Journal of VLSI Design & Communication Systems 5 (3), 1, 2014 | 13 | 2014 |
| A novel efficient adiabatic logic design for ultra low power A Agrawal, TK Gupta, AK Dadoria, D Kumar 2016 International Conference on ICT in Business Industry & Government …, 2016 | 12 | 2016 |
| Design and analysis of low-power adiabatic logic circuits by using CNTFET technology AK Dadoria, K Khare Circuits, Systems, and Signal Processing 38, 4338-4356, 2019 | 11 | 2019 |
| Leakage reduction by using FinFET technique for nanoscale technology circuits AK Dadoria, K Khare, TK Gupta, RP Singh Journal of Nanoelectronics and Optoelectronics 12 (3), 278-285, 2017 | 10 | 2017 |
| Comparative analysis of variable NT sram cells AK Dadoria, AS Yadav, CM Roy International Journal of Advanced Research in Computer Science and Software …, 2013 | 10 | 2013 |
| Sleepy lector: A novel approach for leakage reduction in DSM technology AK Dadoria, K Khare, RP Singh 2016 6th International Conference-Cloud System and Big Data Engineering …, 2016 | 7 | 2016 |
| Comparative analysis of various domino logic circuits for better performance R Thakur, AK Dadoria, TK Gupta 2014 International Conference on Advances in Electronics Computers and …, 2014 | 6 | 2014 |
| Ultra low power high speed domino logic circuit by using FiNFET technology AK Dadoria, K Khare, TK Gupta, RP Singh Advances in Electrical and Electronic Engineering 14 (1), 66-74, 2016 | 5 | 2016 |
| Comparison on different domino logic design for high-performance and leakage-tolerant wide OR gate U Panwar, AK Dadoria International Journal of Engineering Research and Applications 3 (6), 2048-2052, 2013 | 5 | 2013 |
| Integrating flipped drain and power gating techniques for efficient FinFET logic circuits AK Dadoria, K Khare, TK Gupta, U Panwar International Journal of Numerical Modelling: Electronic Networks, Devices …, 2018 | 4 | 2018 |
| Low power high speed 1-bit full adder circuit design in DSM technology A Yadav, BP Shrivastava, AK Dadoria 2017 International Conference on Information, Communication, Instrumentation …, 2017 | 4 | 2017 |
| A New CMOS Voltage Divider Based Current Mirror Compared with the Basic and Cascode Current Mirrors AK Dadoria, AS Yadav, CM Roy International Journal of Advanced Research in Computer Science and Software …, 2013 | 4 | 2013 |
| Design of Low-Power Dynamic Type Latch Comparator Using 18 nm FinFET Technology for SAR ADC B Hemalatha, AK Dadoria Advances in Engineering Design: Select Proceedings of FLAME 2020, 603-609, 2021 | 2 | 2021 |
| New leakage reduction techniques for FinFET technology with its application AK Dadoria, K Khare, TK Gupta, RP Singh Journal of Circuits, Systems and Computers 27 (07), 1850112, 2018 | 2 | 2018 |
