| Efficient VLSI architecture for decimation-in-time fast Fourier transform of real-valued data PK Meher, BK Mohanty, SK Patel, S Ganguly, T Srikanthan IEEE Transactions on Circuits and Systems I: Regular Papers 62 (12), 2836-2845, 2015 | 47 | 2015 |
| A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits S Ganguly, A Mittal, SE Ahmed, MB Srinivas Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on, 69-72, 2014 | 17 | 2014 |
| A Reconfigurable Parallel Prefix Ling Adder with modified Enhanced Flagged Binary logic S Ganguly, A Mittal, SE Ahmed Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference …, 2012 | 6 | 2012 |
| Simulation of NMR implementation of Deutsch-Jozsa algorithm V Chappidi, S Ganguly Advance Computing Conference (IACC), 2014 IEEE International, 838-843, 2014 | | 2014 |
