| Thermal oxide equivalent low temperature ALD oxide for dual purpose gate oxide and method for producing the same S Siddiqui, AN Zainuddin, B Baumert, S Uppal US Patent 10,106,892, 2018 | 309 | 2018 |
| Hybrid bonding interface for 3-dimensional chip integration KW Barth, RA Donaton, S Galis, KS Petrarca, S Siddiqui US Patent 8,159,060, 2012 | 261 | 2012 |
| Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric S Siddiqui, MP Chudzik, CJ Radens US Patent 8,373,239, 2013 | 245 | 2013 |
| High Performance 14nm SOI FinFET CMOS Technology with 0.0174 μ m2 embedded DRAM and 15 Levels of Cu Metallization IEDM, 2014, 2014 | 179* | 2014 |
| A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ... 2011 International Electron Devices Meeting, 28.1. 1-28.1. 4, 2011 | 129 | 2011 |
| Replacement gate MOSFET with self-aligned diffusion contact SH Jain, CJ Radens, S Siddiqui, JW Strane US Patent 8,421,077, 2013 | 76 | 2013 |
| Modification of porous silica particles with poly(acrylic acid) RMO K. Suzuki, S. Siddiqui, C. Chappell, J. A. Siddiqui Polymers for Advanced Technologies - POLYM ADVAN TECHNOL 11 (no. 2), 92-97, 2000 | 53* | 2000 |
| Semiconductor devices having different gate oxide thicknesses CDW Adams, MP Chudzik, SA Krishnan, U Kwon, S Siddiqui US Patent 8,941,177, 2015 | 48 | 2015 |
| Effect of plasma N2 and thermal NH3 nitridation in HfO2 for ultrathin equivalent oxide thickness M Dai, Y Wang, J Shepard, J Liu, M Brodsky, S Siddiqui, P Ronsheim, ... Journal of Applied Physics 113 (4), 2013 | 35 | 2013 |
| Improving yield through the application of process window OPC JT Azpiroz, A Krasnoperova, S Siddiqui, K Settlemyer, I Graur, I Stobert, ... Optical Microlithography XXII 7274, 346-358, 2009 | 23 | 2009 |
| Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices MJ Brodsky, MM Chowdhury, MP Chudzik, M Dai, SA Krishnan, ... US Patent 8,809,152, 2014 | 18 | 2014 |
| Methods and structure to form high K metal gate stack with single work-function metal T Ando, B Kannan, S Krishnan, U Kwon, S Siddiqui US Patent 9,515,164, 2016 | 16 | 2016 |
| Composite high-k gate dielectric stack for reducing gate leakage MJ Brodsky, MP Chudzik, M Dai, JF Shepard Jr, S Siddiqui, Y Wang, J Liu US Patent 9,029,959, 2015 | 13 | 2015 |
| Development or removal of block copolymer or PMMA-bS-based resist using polar supercritical solvent ME Colburn, D Shneyder, S Siddiqui US Patent 7,407,554, 2008 | 11 | 2008 |
| Film planarization for low-k polymers used in semiconductor structures DD Restaino, JC Hedrick, JA Fitzsimmons, CS Tyberg, CC Liu, S Siddiqui US Patent 6,638,878, 2003 | 11 | 2003 |
| Integrated circuit structure having thin gate dielectric device and thick gate dielectric device SA Khan, U Kwon, S Siddiqui, SM Polvino, JF Shepard Jr US Patent 9,806,161, 2017 | 10 | 2017 |
| Higher ‘K’gate dielectric cap for replacement metal gate (RMG) FINFET devices S Siddiqui, B Kannan, S Krishnan US Patent 9,741,720, 2017 | 10 | 2017 |
| TSV deep trench capacitor and anti-fuse structure RG Filippi, E Kaltalioglu, S Siddiqui, PC Wang, L Zhang US Patent 9,741,657, 2017 | 10 | 2017 |
| Multiple thickness gate dielectrics for replacement gate field effect transistors U Kwon, WL Lai, V Narayanan, SM Polvino, R Ramachandran, S Siddiqui US Patent 9,368,593, 2016 | 10 | 2016 |
| Multi-plasma nitridation process for a gate dielectric MP Chudzik, BP Linder, S Siddiqui US Patent 9,006,064, 2015 | 10 | 2015 |
