| Caffeinated FPGAs: FPGA framework for convolutional neural networks R DiCecco, G Lacey, J Vasiljevic, P Chow, G Taylor, S Areibi 2016 International Conference on Field-Programmable Technology (FPT), 265-268, 2016 | 150 | 2016 |
| DART: A programmable architecture for NoC simulation on FPGAs D Wang, NE Jerger, JG Steffan Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on …, 2011 | 99 | 2011 |
| OpenCL library of stream memory components targeting FPGAs J Vasiljevic, R Wittig, P Schumacher, J Fifield, FM Vallina, H Styles, ... 2015 international conference on field programmable technology (FPT), 104-111, 2015 | 16 | 2015 |
| Compute substrate for Software 2.0 J Vasiljevic, L Bajic, D Capalija, S Sokorac, D Ignjatovic, L Bajic, ... IEEE micro 41 (2), 50-55, 2021 | 13 | 2021 |
| Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use J Vasiljevic, P Chow 2014 24th International Conference on Field Programmable Logic and …, 2014 | 10 | 2014 |
| MPack: global memory optimization for stream applications in high-level synthesis J Vasiljevic, P Chow Proceedings of the 2014 ACM/SIGDA international symposium on Field …, 2014 | 4 | 2014 |
| Analysis and architecture design of scalable fractional motion estimation for H. 264 encoding J Vasiljevic, A Ye Integration 45 (4), 427-438, 2012 | 4 | 2012 |
| Processor cores using packet identifiers for routing and computation D Capalija, L Bajic, J Vasiljevic US Patent 11,269,628, 2022 | 3 | 2022 |
| Compute substrate for Software 2.0 L Bajic, J Vasiljevic 2020 IEEE Hot Chips 32 Symposium (HCS), 1-31, 2020 | 2 | 2020 |
| Optimizing an OpenCL Application for Video Watermarking in FPGAs J Vasiljevic, FM Vallina Xcell journal 91, 80, 2015 | 2 | 2015 |
| Application data flow graph execution using network-on-chip overlay J Vasiljevic, D Capalija, Z Moudallal, U Aydonat, J Chu, SA Chin, L Bajic US Patent 11,934,897, 2024 | 1 | 2024 |
| Overlay layer hardware unit for network of processor cores I Matosevic, D Capalija, J Vasiljevic, U Aydonat, SA Chin, D Maksimovic, ... US Patent 11,734,224, 2023 | 1 | 2023 |
| Overlay layer for network of processor cores D Capalija, I Matosevic, J Vasiljevic, U Aydonat, A Lewycky, SA Chin, ... US Patent App. 17/945,045, 2023 | 1 | 2023 |
| Effect of scaling on the area and performance of the H. 264/AVC full-search fractional motion estimation algorithm on field-programmable gate arrays J Vasiljevic, AG Ye IET computers & digital techniques 6 (2), 95-104, 2012 | 1 | 2012 |
| A scalability study of fractional motion estimation for H. 264 encoding J Vasiljevic, A Ye CCECE 2010, 1-5, 2010 | 1 | 2010 |
| Seamless place and route for heterogenous network of processor cores J Vasiljevic, L Bajic, D Capalija, S Sokorac US Patent 11,960,885, 2024 | | 2024 |
| Processor cores using packet identifiers for routing and computation D Capalija, L Bajic, J Vasiljevic US Patent 11,829,752, 2023 | | 2023 |
| Sparsity uniformity enforcement for multicore processor L Bajic, D Capalija, YT Chen, A Grebenisan, H Farooq, A Rakhmati, ... US Patent App. 18/202,252, 2023 | | 2023 |
| Overlay layer hardware unit for network of processor cores I Matosevic, D Capalija, J Vasiljevic, U Aydonat, SA Chin, D Maksimovic, ... US Patent App. 18/196,418, 2023 | | 2023 |
| Runtime predictors for computation reduction in dependent computations L Bajic, D Capalija, YT Chen, A Grebenisan, H Farooq, A Rakhmati, ... US Patent App. 17/589,446, 2023 | | 2023 |
