| Impact of variability on processor performance in negative capacitance finfet technology H Amrouch, G Pahwa, AD Gaidhane, CK Dabhi, F Klemme, O Prakash, ... IEEE Transactions on Circuits and Systems I: Regular Papers 67 (9), 3127-3137, 2020 | 56 | 2020 |
| A simulation study of nbti impact on 14-nm node finfet technology for logic applications: Device degradation to circuit-level interaction S Mishra, H Amrouch, J Joe, CK Dabhi, K Thakor, YS Chauhan, J Henkel, ... IEEE Transactions on Electron Devices 66 (1), 271-278, 2018 | 53 | 2018 |
| Device to circuit framework for activity-dependent nbti aging in digital circuits A Thirunavukkarasu, H Amrouch, J Joe, N Goel, N Parihar, S Mishra, ... IEEE Transactions on Electron Devices 66 (1), 316-323, 2018 | 28 | 2018 |
| Subthermionic negative capacitance ion sensitive field-effect transistor F Bellando, CK Dabhi, A Saeidi, C Gastaldi, YS Chauhan, AM Ionescu Applied Physics Letters 116 (17), 2020 | 23 | 2020 |
| Transistor self-heating: The rising challenge for semiconductor testing O Prakash, CK Dabhi, YS Chauhan, H Amrouch 2021 IEEE 39th VLSI Test Symposium (VTS), 1-7, 2021 | 22 | 2021 |
| Compact modeling of negative-capacitance FDSOI FETs for circuit simulations CK Dabhi, SS Parihar, A Dasgupta, YS Chauhan IEEE Transactions on Electron Devices 67 (7), 2710-2716, 2020 | 19 | 2020 |
| Impact of self-heating on negative-capacitance FinFET: device-circuit interaction O Prakash, G Pahwa, CK Dabhi, YS Chauhan, H Amrouch IEEE Transactions on Electron Devices 68 (4), 1420-1424, 2021 | 18 | 2021 |
| Compact modeling of temperature-dependent gate-induced drain leakage including low-field effects CK Dabhi, AS Roy, YS Chauhan IEEE Transactions on Electron Devices 66 (7), 2892-2897, 2019 | 15 | 2019 |
| Ferroelectric fdsoi fet modeling for memory and logic applications S Chatterjee, S Kumar, A Gaidhane, CK Dabhi, YS Chauhan, H Amrouch Solid-State Electronics 200, 108554, 2023 | 12 | 2023 |
| NBTI-related variability impact on 14-nm node FinFET SRAM performance and static power: Correlation to time zero fluctuations S Mishra, N Parihar, R Anandkrishnan, CK Dabhi, YS Chauhan, ... IEEE Transactions on Electron Devices 65 (11), 4846-4853, 2018 | 12 | 2018 |
| A unified flicker noise model for FDSOI MOSFETs including back-bias effect P Kushwaha, H Agarwal, CK Dabhi, YK Lin, JP Duarte, C Hu, ... 2018 IEEE International Conference on Electronics, Computing and …, 2018 | 10 | 2018 |
| BSIM4. 6.4 MOSFET Model: User’s Manual C Hu, AM Nikenjad, W Yang, D Lu UC Berkeley, 2009 | 10 | 2009 |
| Novel fdsoi-based dynamic xnor logic for ultra-dense highly-efficient computing S Kumar, S Chatterjee, CK Dabhi, H Amrouch, YS Chauhan 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 3373-3377, 2022 | 9 | 2022 |
| BSIM4 4.8. 1 MOSFET model CK Dabhi, A Dasgupta, H Agrawal, N Paydavosi Dept. Elect. Eng. Comput. Sci., Univ. California, Berkeley, CA, Tech. Rep …, 2017 | 8 | 2017 |
| Underlap channel silicon-on-insulator quantum dot floating-gate MOSFET for low-power memory applications CT Dabhi, GC Patil Journal of Computational Electronics 15 (4), 1563-1569, 2016 | 6 | 2016 |
| Modeling of induced gate thermal noise including back-bias effect in FDSOI MOSFET CK Dabhi, A Dasgupta, P Kushwaha, H Agarwal, C Hu, YS Chauhan IEEE Microwave and Wireless Components Letters 28 (7), 597-599, 2018 | 5 | 2018 |
| Anomalous GIDL effect with back bias in FinFET: Physical insights and compact modeling CK Dabhi, AS Roy, L Yang, YS Chauhan IEEE Transactions on Electron Devices 68 (7), 3261-3267, 2021 | 4 | 2021 |
| Physical analysis of non-monotonic DIBL dependence on back gate bias in thick front gate oxide FDSOI MOSFETs CK Dabhi, P Kushwaha, H Agarwal, SS Chauhan, C Hu, YS Chauhan 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2019 | 4 | 2019 |
| Fabrication and investigation of low-voltage programmable flash memory gate stack R Dhavse, K Prashant, C Dabhi, A Darji, RM Patrikar Proceedings of the International Conference on Microelectronics, Computing …, 2018 | 4 | 2018 |
| Non-traditional design of dynamic logics using fdsoi for ultra-efficient computing S Kumar, S Chatterjee, CK Dabhi, YS Chauhan, H Amrouch IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2023 | 3 | 2023 |
Yogesh S. ChauhanFellow IEEE, FNAE, Professor-IIT KanpurVerified email at iitk.ac.in
