| Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes V Bharath Sreenivasulu, V Narendar Microelectronics Journal 116, 105214, 2021 | 56 | 2021 |
| Design insights of nanosheet FET and CMOS circuit applications at 5-nm technology node V Bharath Sreenivasulu, V Narendar IEEE Transactions on Electron Devices 69 (8), 4115-4122, 2022 | 51 | 2022 |
| A comprehensive analysis of junctionless tri-gate (TG) FinFET towards low-power and high-frequency applications at 5-nm gate length V Bharath Sreenivasulu, V Narendar Silicon, 1-13, 2021 | 51 | 2021 |
| Design and temperature assessment of junctionless nanosheet FET for nanoscale applications VB Sreenivasulu, V Narendar Silicon 14 (8), 3823-3834, 2022 | 41 | 2022 |
| Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length V Bharath Sreenivasulu, V Narendar AEU-International Journal of Electronics and Communications 137, 153803, 2021 | 37 | 2021 |
| Junctionless SOI FinFET with Advanced Spacer Techniques for sub-3 nm Technology Nodes V Bharath Sreenivasulu, V Narendar AEUE - International Journal of Electronics and Communications 145, 154069, 2022 | 36 | 2022 |
| Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications V Bharath Sreenivasulu, V Narendar ECS Journal of Solid State Science and Technology 10 (1), 013008, 2021 | 36 | 2021 |
| Design insights into RF/analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications V Bharath Sreenivasulu, V Narendar International Journal of RF and Microwave Computer‐Aided Engineering 31 (12 …, 2021 | 29 | 2021 |
| Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs AS Kumar, M Deekshana, VB Sreenivasulu, RP Somineni, DK Sudha 2022 13th International Conference on Computing Communication and Networking …, 2022 | 28 | 2022 |
| Junctionless gate-all-around nanowire FET with asymmetric spacer for continued scaling VB Sreenivasulu, V Narendar Silicon 14 (13), 7461-7471, 2022 | 23 | 2022 |
| p-Type trigate junctionless nanosheet MOSFET: analog/RF, linearity, and circuit analysis BS Vakkalakula, N Vadthiya ECS Journal of Solid State Science and Technology 10 (12), 123001, 2021 | 22 | 2021 |
| Circuit analysis and optimization of GAA nanowire FET towards low power and high switching VB Sreenivasulu, V Narendar Silicon 14 (16), 10401-10411, 2022 | 20 | 2022 |
| Common source amplifier and ring oscillator circuit performance optimization using multi-bridge channel FETs V Bharath Sreenivasulu, NA Kumari, V Lokesh, SK Vishvakarma, ... ECS Journal of Solid State Science and Technology 12 (2), 023013, 2023 | 17 | 2023 |
| Impact of scaling on nanosheet FET and CMOS circuit applications NA Kumari, VB Sreenivasulu, P Prithvi ECS Journal of Solid State Science and Technology 12 (3), 033001, 2023 | 13 | 2023 |
| Design of approximate reverse carry select adder using RCPA R Turaka, KR Bonagiri, TS Rao, GK Kumar, S Jayabalan, ... International Journal of Electronics Letters 11 (2), 146-156, 2023 | 10 | 2023 |
| Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison VB Sreenivasulu, NA Kumari, SR Kola, J Singh, Y Li IEEE Access, 2023 | 9 | 2023 |
| LG 55 nm T‐gate InGaN/GaN channel based high electron mobility transistors for stable transconductance operation R Angamuthu, B ChettiaGoundar Sengodan, M Anandan, A Varghese, ... International Journal of RF and Microwave Computer‐Aided Engineering 32 (10 …, 2022 | 9 | 2022 |
| Concurrent error detectable and self-repairable carry select adder S Musala, AK Neelam, B Sreenivasulu V, KV Vardhan International Journal of Electronics 109 (11), 1954-1972, 2022 | 9 | 2022 |
| Self-Heating and Interface Traps Assisted Early Aging Revelation and Reliability Analysis of Negative Capacitance FinFET RK Jaisawal, S Rathore, N Gandhi, PN Kondekar, S Banchhor, ... 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2023 | 8 | 2023 |
| Design of Resistive Load Inverter and Common Source Amplifier Circuits Using Symmetric and Asymmetric Nanowire FETs VB Sreenivasulu, NA Kumari, V Lokesh, J Ajayan, M Uma Journal of Electronic Materials 52 (11), 7268-7279, 2023 | 6 | 2023 |
Vadthiya NarendarNational Institute of Technology WarangalVerified email at nitw.ac.in
