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Rahul Agarwal
Rahul Agarwal
Verified email at microsoft.com
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Year
Design issues and considerations for low-cost 3-D TSV IC technology
G Van der Plas, P Limaye, I Loi, A Mercha, H Oprins, C Torregiani, S Thijs, ...
Solid-State Circuits, IEEE Journal of 46 (1), 293-307, 2011
3882011
Cu/Sn microbumps interconnect for 3D TSV chip stacking
R Agarwal, W Zhang, P Limaye, R Labie, B Dimcic, A Phommahaxay, ...
2010 Proceedings 60th electronic components and technology conference (ECTC …, 2010
1122010
High density Cu-Sn TLP bonding for 3D integration
R Agarwal, W Zhang, P Limaye, W Ruythooren
2009 59th electronic components and technology conference, 345-349, 2009
512009
Fabrication of vertical mirrors using plasma etch and KOH: IPA polishing
R Agarwal, S Samson, S Bhansali
Journal of Micromechanics and Microengineering 17 (1), 26, 2006
462006
3D packaging for heterogeneous integration
R Agarwal, P Cheng, P Shah, B Wilkerson, R Swaminathan, J Wuu, ...
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 1103-1107, 2022
382022
3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU
J Wuu, R Agarwal, M Ciraula, C Dietz, B Johnson, D Johnson, ...
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 428-429, 2022
342022
Insertion bonding: A novel Cu-Cu bonding approach for 3D integration
C Okoro, R Agarwal, P Limaye, B Vandevelde, D Vandepitte, E Beyne
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC …, 2010
322010
Molded chip combination
MS Bhagavat, L Fu, I Barber, CK Leong, R Agarwal
US Patent 10,510,721, 2019
272019
Die stacking using 3D-wafer level packaging copper/polymer through-Si via technology and Cu/Sn interconnect bumping
Y Civale, DS Tezcan, HGG Philipsen, P Jaenen, R Agarwal, F Duval, ...
2009 IEEE International Conference on 3D System Integration, 1-4, 2009
272009
Die stacking for multi-tier 3D integration
R Agarwal, MS Bhagavat
US Patent 10,727,204, 2020
262020
Fabrication of integrated vertical mirror surfaces and transparent window for packaging MEMS devices
R Agarwal, S Samson, S Kedia, S Bhansali
Journal of Microelectromechanical systems 16 (1), 122-129, 2007
262007
Device performance analysis on 20nm technology thin wafers in a 3D package
S Kannan, R Agarwal, A Bousquet, G Aluri, HS Chang
2015 IEEE International Reliability Physics Symposium, 4C. 4.1-4C. 4.5, 2015
202015
Enhancing rankings of search results for member profile queries
R Agarwal, S Sundaram
US Patent 10,042,940, 2018
192018
Chip-package interaction: Challenges and solutions to mechanical stability of Back end of Line at 28nm node and beyond for advanced flip chip application
F Kuechenmeister, D Breuer, H Geisler, J Paul, C Shah, KV Machani, ...
2012 IEEE 14th Electronics Packaging Technology Conference (EPTC), 430-436, 2012
182012
A three-axis SOI accelerometer sensing with both in-plane and vertical comb electrodes
J Xie, R Agarwal, Y Liu, JM Tsai
Microsystem technologies 18, 325-332, 2012
182012
Enabling 10µm pitch hybrid Cu-Cu IC stacking with Through Silicon Vias
C Huyghebaert, J Van Olmen, O Chukwudi, J Coenen, A Jourdain, ...
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC …, 2010
182010
Fabrication processes for packaged optical MEMS devices
S Samson, R Agarwal, S Kedia, W Wang, S Onishi, J Bumgarner
2005 International Conference on MEMS, NANO and Smart Systems, 113-118, 2005
172005
Compact electrode design for an in-plane accelerometer on SOI with refilled isolation trench
J Xie, R Agarwal, Y Liu, JM Tsai, N Ranganathan, J Singh
Journal of Micromechanics and Microengineering 21, 095005, 2011
162011
Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack-Challenges and solutions
G Van der Plas, S Thijs, D Linten, G Katti, P Limaye, A Mercha, M Stucchi, ...
IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010
162010
Comparison of microchannel dimensions for air-breathing polymer exchange membrane microfuel cells
CS Spiegel, R Agarwal, S Bhansali
Journal of power sources 182 (2), 603-608, 2008
162008
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