| A modified capacitance model of RF MEMS shunt switch incorporating fringing field effects of perforated beam K Guha, M Kumar, S Agarwal, S Baishya Solid-State Electronics 114, 35-42, 2015 | 48 | 2015 |
| A subthreshold surface potential model for short-channel MOSFET taking into account the varying depth of channel depletion layer due to source and drain junctions S Baishya, A Mallik, CK Sarkar IEEE transactions on electron devices 53 (3), 507-514, 2006 | 45 | 2006 |
| Heterojunction fully depleted SOI-TFET with oxide/source overlap S Chander, B Bhowmick, S Baishya Superlattices and Microstructures 86, 43-50, 2015 | 39 | 2015 |
| A tunneling current density model for ultra thin HfO2 high-k dielectric material based MOS devices NP Maity, R Maity, RK Thapa, S Baishya Superlattices and Microstructures 95, 24-32, 2016 | 36 | 2016 |
| A two-dimensional gate threshold voltage model for a heterojunction SOI-tunnel FET with oxide/source overlap S Chander, S Baishya IEEE Electron device letters 36 (7), 714-716, 2015 | 35 | 2015 |
| Temperature effect on RF/analog and linearity parameters in DMG FinFET R Saha, B Bhowmick, S Baishya Applied Physics A 124 (9), 1-10, 2018 | 31 | 2018 |
| Study of interface charge densities for zro2 and hfo2 based metal-oxide-semiconductor devices NP Maity, R Maity, RK Thapa, S Baishya Advances in Materials Science and Engineering 2014, 2014 | 31 | 2014 |
| Voltage and oxide thickness dependent tunneling current density and tunnel resistivity model: application to high-k material HfO2 based MOS devices NP Maity, R Maity, S Baishya Superlattices and Microstructures 111, 628-641, 2017 | 30 | 2017 |
| Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation NP Maity, R Maity, S Maity, S Baishya Journal of Computational Electronics 18 (2), 492-499, 2019 | 29 | 2019 |
| Tri-gate heterojunction SOI Ge-FinFETs R Das, R Goswami, S Baishya Superlattices and Microstructures 91, 51-61, 2016 | 29 | 2016 |
| A model for doubly clamped piezoelectric energy harvesters with segmented electrodes R Kashyap, TR Lenka, S Baishya IEEE Electron Device Letters 36 (12), 1369-1372, 2015 | 29 | 2015 |
| Electrical noise in circular gate tunnel FET in presence of interface traps R Goswami, B Bhowmick, S Baishya Superlattices and Microstructures 86, 342-354, 2015 | 29 | 2015 |
| Performance analysis of RF MEMS capacitive switch with non uniform meandering technique K Guha, M Kumar, A Parmar, S Baishya Microsystem Technologies 22 (11), 2633-2640, 2016 | 27 | 2016 |
| Statistical dependence of gate metal work function on various electrical parameters for an n-channel Si step-FinFET R Saha, B Bhowmick, S Baishya IEEE Transactions on Electron Devices 64 (3), 969-976, 2017 | 25 | 2017 |
| Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs S Chander, S Baishya, SK Sinha, S Kumar, PK Singh, K Baral, ... Superlattices and Microstructures 131, 30-39, 2019 | 23 | 2019 |
| Impact of thin high-k dielectrics and gate metals on RF characteristics of 3D double gate junctionless transistor A Baidya, S Baishya, TR Lenka Materials Science in Semiconductor Processing 71, 413-420, 2017 | 23 | 2017 |
| Effect of scaling on noise in circular gate TFET and its application as a digital inverter R Goswami, B Bhowmick, S Baishya Microelectronics Journal 53, 16-24, 2016 | 23 | 2016 |
| Image force effect on tunneling current for ultra thin high-K dielectric material Al2O3 based metal oxide semiconductor devices NP Maity, R Maity, RK Thapa, S Baishya Journal of Nanoelectronics and Optoelectronics 10 (5), 645-648, 2015 | 23 | 2015 |
| A pseudo two-dimensional subthreshold surface potential model for dual-material gate MOSFETs S Baishya, A Mallik, CK Sarkar IEEE Transactions on Electron Devices 54 (9), 2520-2525, 2007 | 22 | 2007 |
| An analytical model for the surface potential and threshold voltage of a double-gate heterojunction tunnel FinFET NP Maity, R Maity, S Baishya Journal of computational electronics 18 (1), 65-75, 2019 | 21 | 2019 |
Koushik GuhaNational Institute of Technology SilcharVerified email at ece.nits.ac.in
