| A Physical Model of the Temperature Dependence of the Current Through Stacks L Vandelli, A Padovani, L Larcher, RG Southwick, WB Knowlton, ... IEEE Transactions on Electron Devices 58 (9), 2878-2887, 2011 | 268 | 2011 |
| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 174 | 2016 |
| Stacked dual-oxide MOS energy band diagram visual representation program (IRW student paper) RG Southwick, WB Knowlton IEEE Transactions on Device and Materials Reliability 6 (2), 136-145, 2006 | 112 | 2006 |
| A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI KI Seo, B Haran, D Gupta, D Guo, T Standaert, R Xie, H Shang, E Alptekin, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 108 | 2014 |
| Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio DK Mohata, R Bijesh, Y Zhu, MK Hudait, R Southwick, Z Chbili, ... 2012 Symposium on VLSI technology (VLSIT), 53-54, 2012 | 81 | 2012 |
| Limitations of Poole–Frenkel Conduction in Bilayer MOS Devices RG Southwick, J Reed, C Buu, R Butler, G Bersuker, WB Knowlton IEEE Transactions on Device and materials reliability 10 (2), 201-207, 2009 | 72 | 2009 |
| Ultrafast measurements and physical modeling of NBTI stress and recovery in RMG FinFETs under diverse DC–AC experimental conditions N Parihar, U Sharma, RG Southwick, M Wang, JH Stathis, S Mahapatra IEEE Transactions on Electron Devices 65 (1), 23-30, 2017 | 71 | 2017 |
| An interactive simulation tool for complex multilayer dielectric devices RG Southwick, A Sup, A Jain, WB Knowlton IEEE Transactions on Device and Materials Reliability 11 (2), 236-243, 2011 | 71 | 2011 |
| FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 65 | 2016 |
| Total ionizing dose radiation effects on 14 nm FinFET and SOI UTBB technologies H Hughes, P McMarr, M Alles, E Zhang, C Arutt, B Doris, D Liu, ... 2015 IEEE Radiation Effects Data Workshop (REDW), 1-6, 2015 | 62 | 2015 |
| Modeling of NBTI kinetics in RMG Si and SiGe FinFETs, part-I: DC stress and recovery N Parihar, RG Southwick, M Wang, JH Stathis, S Mahapatra IEEE Transactions on Electron Devices 65 (5), 1699-1706, 2018 | 47 | 2018 |
| A 14 nm embedded stt-mram cmos technology D Edelstein, M Rizzolo, D Sil, A Dutta, J DeBrosse, M Wordeman, A Arceo, ... 2020 IEEE International Electron Devices Meeting (IEDM), 11.5. 1-11.5. 4, 2020 | 44 | 2020 |
| Reliability challenges for the 10nm node and beyond JH Stathis, M Wang, RG Southwick, EY Wu, BP Linder, EG Liniger, ... 2014 IEEE International Electron Devices Meeting, 20.6. 1-20.6. 4, 2014 | 43 | 2014 |
| Selective GeOx-scavenging from interfacial layer on Si1−xGex channel for high mobility Si/Si1−xGex CMOS application CH Lee, H Kim, P Jamison, RG Southwick, S Mochizuki, K Watanabe, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 32 | 2016 |
| A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies B DeSalvo, P Morin, M Pala, G Ghibaudo, O Rozeau, Q Liu, A Pofelski, ... 2014 IEEE international electron devices meeting, 7.2. 1-7.2. 4, 2014 | 32 | 2014 |
| A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs T Yamashita, S Mehta, VS Basker, R Southwick, A Kumar, ... 2015 Symposium on VLSI Technology (VLSI Technology), T154-T155, 2015 | 30 | 2015 |
| Modeling of NBTI kinetics in replacement metal gate Si and SiGe FinFETs—Part-II: AC stress and recovery N Parihar, RG Southwick, M Wang, JH Stathis, S Mahapatra IEEE Transactions on Electron Devices 65 (5), 1707-1713, 2018 | 28 | 2018 |
| A comparative study of strain and Ge content in Si1−xGex channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs CH Lee, S Mochizuki, RG Southwick, J Li, X Miao, R Bao, T Ando, ... 2017 IEEE International Electron Devices Meeting (IEDM), 37.2. 1-37.2. 4, 2017 | 23 | 2017 |
| SiGe composition and thickness effects on NBTI in replacement metal gate/high-κ technologies P Srinivasan, J Fronheiser, K Akarvardar, A Kerber, LF Edge, ... 2014 IEEE International Reliability Physics Symposium, 6A. 3.1-6A. 3.6, 2014 | 23 | 2014 |
| Comparison of DC and AC NBTI kinetics in RMG Si and SiGe p-FinFETs N Parihar, RG Southwick, U Sharma, M Wang, JH Stathis, S Mahapatra 2017 IEEE International Reliability Physics Symposium (IRPS), 2D-4.1-2D-4.7, 2017 | 21 | 2017 |
