Alok Garg
Alok Garg
AMD, University of Rochester
Verified email at amd.com
Title
Cited by
Cited by
Year
An intra-chip free-space optical interconnect
J Xue, A Garg, B Ciftcioglu, J Hu, S Wang, I Savidis, M Jain, R Berman, ...
ACM SIGARCH Computer Architecture News 38 (3), 94-105, 2010
982010
A performance-correctness explicitly-decoupled architecture
A Garg, MC Huang
2008 41st IEEE/ACM International Symposium on Microarchitecture, 306-317, 2008
502008
Injection-locked clocking: A low-power clock distribution scheme for high-performance microprocessors
L Zhang, A Carpenter, B Ciftcioglu, A Garg, M Huang, H Wu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (9 …, 2008
392008
A 3-D integrated intrachip free-space optical interconnect for many-core chips
B Ciftcioglu, R Berman, J Zhang, Z Darling, S Wang, J Hu, J Xue, A Garg, ...
IEEE Photonics Technology Letters 23 (3), 164-166, 2010
372010
Slackened memory dependence enforcement: Combining opportunistic forwarding with decoupled verification
A Garg, MW Rashid, M Huang
33rd International Symposium on Computer Architecture (ISCA'06), 142-154, 2006
282006
Software-hardware cooperative memory disambiguation
R Huang, A Garg, M Huang
The Twelfth International Symposium on High-Performance Computer …, 2006
262006
Speculative parallelization in decoupled look-ahead
A Garg, R Parihar, MC Huang
2011 International Conference on Parallel Architectures and Compilation …, 2011
172011
Substituting associative load queue with simple hash tables in out-of-order microprocessors
A Garg, F Castro, M Huang, D Chaver, L Pinuel, M Prieto
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power …, 2006
112006
An intra-chip free-space optical interconnect: Extended technical report
J Xue, A Garg, B Ciftcioglu, J Hu, S Wang, I Savidis, M Jain, R Berman, ...
Technical report, Dept. Electrical & Computer Engineering, Univ. of Rochester, 2010
72010
Soft error fault tolerant systems: cs456 survey
A Garg
URL: www. csc. ncsu. edu/faculty/xie/softerrors. html, 2005
62005
Replacing associative load queues: a timing-centric approach
F Castro, R Noor, A Garg, D Chaver, MC Huang, L Pinuel, M Prieto, ...
IEEE Transactions on Computers 58 (4), 496-511, 2008
52008
Dynamic evaluation and reconfiguration of a data prefetcher
SD Bade, A Garg, J Kalamatianos, P Keltcher, M Evers, C Narasimhaiah
US Patent 9,058,277, 2015
32015
Injection-locked clocking: A low-power clock distribution scheme for high-end microprocessors
H Wu, L Zhang, A Carpenter, A Garg, M Huang
Proc. of the 3rd Watson Conference on Interaction between Architecture …, 2006
22006
Implementing software-hardware cooperative memory disambiguation
A Garg, R Huang, M Huang
Technical Report, 2005
22005
Exploring performance-correctness explicitly-decoupled architectures
A Garg
University of Rochester, 2011
12011
Implementation Issues of Slackened Memory Dependence Enforcement
A Garg, M Rashid, M Huang
Technical report, Electrical & Computer Engineering Department, University …, 2006
12006
SCHEDULER QUEUE ASSIGNMENT BURST MODE
A Garg, SA Mclelland, M Evers, MT Sobel
US Patent App. 16/709,527, 2021
2021
Multi-class multi-label classification using clustered singular decision trees for hardware adaptation
J Kalamatianos, PS Keltcher, M Chhablani, A Garg, F Eris
US Patent App. 16/454,027, 2020
2020
Scheduler queue assignment
MT Sobel, DA Priore, A Garg
US Patent App. 15/991,088, 2019
2019
Predictive multistage comparison for associative memory
CD Henrion, MK Ciraula, G Donley, A Garg, E Busta
US Patent 9,916,246, 2018
2018
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