| Transition probabilistic approach for detection and diagnosis of Hardware Trojan in combinational circuits J Popat, U Mehta 2016 IEEE Annual India Conference (INDICON), 1-6, 2016 | 11 | 2016 |
| Statistical security analysis of AES with X‐tolerant response compactor against all types of test infrastructure attacks with/without novel unified countermeasure J Popat, U Mehta IET Circuits, Devices & Systems 13 (8), 1117-1124, 2019 | 5 | 2019 |
| A novel countermeasure against differential scan attack in AES algorithm J Popat, U Mehta VLSI Design and Test: 22nd International Symposium, VDAT 2018, Madurai …, 2019 | 5 | 2019 |
| Power reduction techniques used in testing of VLSI circuits J Shaktisinh, J Popat, R Patel 2015 Annual IEEE India Conference (INDICON), 1-4, 2015 | 4 | 2015 |
| A Review on Operational Transconductance Amplifier (OTA) Using 180nm Technology MU Vadodaria, R Patel, J Popat International Journal of Advance Engineering and Research Development 1 (11 …, 2014 | 2 | 2014 |
| Transition probability-based detection of hardware trojan in digital circuits U Mehta, J Popat Proceedings of Sixth International Congress on Information and Communication …, 2022 | 1 | 2022 |
| Design and Implementation of High Gain, High Unity Gain Bandwidth, High Slew Rate and Low Power Dissipation CMOS Folded Cascode OTA for Wide Band Applications MU Vadodaria, R Patel, J Popat Journal of Electrical and Electronic Systems 4 (2), 2015 | 1 | 2015 |
| A review on low power testing techniques S Jadeja, P Mathuria, J Popat Proc of International Journal of Advanced Networking Applications, 70-72, 2015 | 1 | 2015 |
| Defense against Security Threats with Regard to SoC Life Cycle U Mehta, J Popat Frontiers of Quality Electronic Design (QED) AI, IoT and Hardware Security …, 2023 | | 2023 |
| A Hash based Secure Scheme (HSS) against scanbased attacks on AES cipher J Popat, U Mehta, M Upadhyay 2020 IEEE International Test Conference India, 1-4, 2020 | | 2020 |
| Hardware Security in Case of Scan Based Attack on Crypto Hardware J Popat, U Mehta International Journal of VLSI design & Communication Systems (VLSICS) Vol 9, 2018 | | 2018 |
| Design Procedure for Low Dropout Voltage Regulator for Portable Devices Application N Rathod, J Popat, DG Patanvariya Programmable Device Circuits and Systems, 117-122, 2017 | | 2017 |
| Speed Optimized AES Algorithm on Re-Configurable Hardware A Gondaliya, J Popat Programmable Device Circuits and Systems 8 (6), 172-176, 2016 | | 2016 |
| Analysis of Power Reduction Techniques used in Testing of VLSI Circuits SK Jadeja, R Patel, J Popat Journal of Electrical & Electronics 4 (2), 1, 2015 | | 2015 |
| A Review on Various Hardware Architectures of AES Algorithm A Gondaliya, J Popat Programmable Device Circuits and Systems, 297-300, 2015 | | 2015 |
