| Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement PV Bhanu, PV Kulkarni, J Soumya ACM Journal on Emerging Technologies in Computing Systems (JETC) 15 (1), 23, 2019 | 20 | 2019 |
| Multi-application based network-on-chip design for mesh-of-tree topology using global mapping and reconfigurable architecture M Upadhyay, M Shah, PV Bhanu, J Soumya, LR Cenkeramaddi 2019 32nd international conference on VLSI Design and 2019 18th …, 2019 | 17 | 2019 |
| Fault-tolerant application mapping on mesh-of-tree based network-on-chip PV Bhanu, J Soumya Journal of Systems Architecture 116, 102026, 2021 | 14 | 2021 |
| Flexible spare core placement in torus topology based nocs and its validation on an fpga PV Bhanu, R Govindan, P Kattamuri, J Soumya, LR Cenkeramaddi IEEE Access 9, 45935-45954, 2021 | 12 | 2021 |
| Fault-tolerant routing algorithm for mesh based NoC using reinforcement learning J Samala, H Takawale, Y Chokhani, PV Bhanu, J Soumya 2020 24th International Symposium on VLSI Design and Test (VDAT), 1-6, 2020 | 12 | 2020 |
| Noc application mapping optimization using reinforcement learning S Jagadheesh, PV Bhanu ACM Transactions on Design Automation of Electronic Systems (TODAES) 27 (6 …, 2022 | 9 | 2022 |
| Reinforcement learning based fault-tolerant routing algorithm for mesh based noc and its fpga implementation S Jagadheesh, PV Bhanu, J Soumya, LR Cenkeramaddi IEEE Access 10, 44724-44737, 2022 | 8 | 2022 |
| Torus topology based fault-tolerant network-on-chip design with flexible spare core placement PV Bhanu, P Kulkarni, J Soumya, LR Cenkarmaddi, H Idsøe 2018 14th conference on Ph. D. research in microelectronics and electronics …, 2018 | 8 | 2018 |
| Fault-tolerant application-specific topology-based NoC and its prototype on an FPGA PV Bhanu, R Govindan, R Kumar, V Singh, J Soumya, LR Cenkeramaddi IEEE Access 9, 76759-76779, 2021 | 4 | 2021 |
| Butterfly-Fat-Tree Topology-Based Fault-Tolerant Network-on-Chip Design Using Particle Swarm Optimization PV Bhanu, PV Kulkarni, UA Kumar, J Soumya Harmony Search and Nature Inspired Optimization Algorithms, 1165-1175, 2019 | 4 | 2019 |
| Fault-tolerant application mapping on to ZMesh topology based network-on-chip design PV Bhanu, N Mandapati, J Soumya, LR Cenkeramaddi 2020 15th IEEE Conference on Industrial Electronics and Applications (ICIEA …, 2020 | 3 | 2020 |
| FILA: Fault-model for interconnection links in application-specific network-on-chip design PV Bhanu, C Vudadha, J Soumya 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 3 | 2020 |
| A Link Fault Tolerant Routing Algorithm for Mesh of Tree Based Network-on-Chips J Pushparaj, PV Bhanu, J Soumya 2019 IEEE International Symposium on Smart Electronic Systems (iSES …, 2019 | 3 | 2019 |
| A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips M Shah, M Upadhyay, PV Bhanu, J Soumya, LR Cenkeramaddi Communications in Computer and Information Science 892, 446-459, 2019 | 3 | 2019 |
| Multi-application based fault-tolerant network-on-chip design for mesh topology using reconfigurable architecture P Veda Bhanu, PV Kulkarni, SP Avadhanam, J Soumya, ... VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019 | 3 | 2019 |
| Fault tolerant routing methodology for mesh-of-tree based network-on-chips using local reconfiguration M Upadhyay, M Shah, PV Bhanu, J Soumya, LR Cenkeramaddi 2018 International Conference on High Performance Computing & Simulation …, 2018 | 3 | 2018 |
| Novel fault-tolerant routing technique for ZMesh topology based network-on-chip design PV Bhanu, V Govil, S Jagadeesh, J Soumya, LR Cenkeramaddi 2020 15th IEEE Conference on Industrial Electronics and Applications (ICIEA …, 2020 | 2 | 2020 |
| Design Automation of Network-on-Chip Prototype on FPGA D Mahajan, S Patil, WV Shashikant, M Dangayach, PV Bhanu, J Soumya 2019 IEEE International Conference on Distributed Computing, VLSI …, 2019 | 2 | 2019 |
| Fault-tolerant network-on-chip design for mesh-of-tree topology using particle swarm optimization PV Bhanu, P Kulkarni, S Jain, J Soumya, LR Cenkarmaddi, H Idsøe TENCON 2018-2018 IEEE Region 10 Conference, 2384-2389, 2018 | 2 | 2018 |
| FPGA Implementation of Novel Routing Algorithm for Butterfly-Fat-Tree Topology based NoC Design PV Bhanu, S Jagadheesh, V Bhat, G Agarwal, J Soumya 2019 15th Conference on Ph. D Research in Microelectronics and Electronics …, 2019 | 1 | 2019 |
Soumya JAssociate Professor at BITS Pilani, Hyderabad CampusVerified email at hyderabad.bits-pilani.ac.in
