PUNEET GUPTA
PUNEET GUPTA
UCLA Electrical and Computer Engineering
Verified email at g.ucla.edu - Homepage
Title
Cited by
Cited by
Year
Trading accuracy for power with an underdesigned multiplier architecture
P Kulkarni, P Gupta, M Ercegovac
2011 24th Internatioal Conference on VLSI Design, 346-351, 2011
4172011
Gate-length biasing for digital circuit optimization
P Gupta, AB Kahng
US Patent 7,441,211, 2008
2482008
Method for correcting a mask design layout
AB Kahng, P Gupta, D Sylvester, J Yang
US Patent 7,149,999, 2006
2422006
Method of IC fabrication, IC mask fabrication and program product therefor
P Gupta, FL Heng, MA Lavin
US Patent 7,353,492, 2008
2192008
Reliable on-chip systems in the nano-era: Lessons learnt and future trends
J Henkel, L Bauer, N Dutt, P Gupta, S Nassif, M Shafique, M Tahoori, ...
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-10, 2013
2012013
Manufacturing-aware physical design
P Gupta, AB Kahng
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
1622003
Underdesigned and opportunistic computing in presence of hardware variability
P Gupta, Y Agarwal, L Dolecek, N Dutt, RK Gupta, R Kumar, S Mitra, ...
IEEE Transactions on Computer-Aided Design of integrated circuits and …, 2012
1362012
Method and system for placing layout objects in a standard-cell layout
P Gupta, AB Kahng, CH Park
US Patent 7,640,522, 2009
1302009
Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI
Y Cao, P Gupta, AB Kahng, D Sylvester, J Yang
15th Annual IEEE International ASIC/SOC Conference, 411-415, 2002
1252002
Methods for gate-length biasing using annotation data
P Gupta, AB Kahng
US Patent 8,185,865, 2012
1222012
Trading accuracy for power in a multiplier architecture
P Kulkarni, P Gupta, MD Ercegovac
Journal of Low Power Electronics 7 (4), 490-501, 2011
1212011
Gate-length biasing for runtime-leakage control
P Gupta, AB Kahng, P Sharma, D Sylvester
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
1202006
Integrated circuit logic with self compensating block delays
P Gupta, FL Heng, DS Kung, DL Ostapko
US Patent 7,084,476, 2006
1102006
Toward a systematic-variation aware timing methodology
P Gupta, FL Heng
Proceedings of the 41st annual Design Automation Conference, 321-326, 2004
1082004
Selective gate-length biasing for cost-effective runtime leakage control
P Gupta, AB Kahng, P Sharma, D Sylvester
Proceedings of the 41st annual Design Automation Conference, 327-330, 2004
1072004
Manufacturing-aware design methodology for assist feature correctness
P Gupta, AB Kahng, CH Park
Design and Process Integration for Microelectronic Manufacturing III 5756 …, 2005
932005
On the efficacy of NBTI mitigation techniques
TB Chan, J Sartori, P Gupta, R Kumar
2011 Design, Automation & Test in Europe, 1-6, 2011
832011
Performance-impact limited area fill synthesis
Y Chen, P Gupta, AB Kahng
Proceedings of the 40th annual Design Automation Conference, 22-27, 2003
742003
Comparative evaluation of spin-transfer-torque and magnetoelectric random access memory
S Wang, H Lee, F Ebrahimi, PK Amiri, KL Wang, P Gupta
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 (2 …, 2016
692016
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability
L Cheng, P Gupta, CJ Spanos, K Qian, L He
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
632011
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