upasana .....
upasana .....
University of Delhi South Campus
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Simulation study for dual material gate hetero-dielectric TFET: Static performance analysis for analog applications
R Narang, M Gupta, M Saxena
2013 Annual IEEE India Conference (INDICON), 1-6, 2013
Switching performance analyses of gate material and gate dielectric engineered TFET architectures and impact of interface oxide charges
R Narang, M Saxena, M Gupta
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS), 1-6, 2014
Linearity and analog performance realization of energy-efficient TFET-based architectures: an optimization for RFIC design
Upasana, R Narang, M Saxena, M Gupta
IETE Technical Review 33 (1), 23-28, 2016
Surface potential based analytical model for hetero-dielectric pnin double-gate tunnel-FET
R Narang, M Saxena, M Gupta
Physics of Semiconductor Devices: 17th International Workshop on the Physics …, 2014
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