| Simulation study for dual material gate hetero-dielectric TFET: Static performance analysis for analog applications R Narang, M Gupta, M Saxena 2013 Annual IEEE India Conference (INDICON), 1-6, 2013 | 22 | 2013 |
| Linearity and analog performance realization of energy-efficient TFET-based architectures: an optimization for RFIC design Upasana, R Narang, M Saxena, M Gupta IETE Technical Review 33 (1), 23-28, 2016 | 9 | 2016 |
| Switching performance analyses of gate material and gate dielectric engineered TFET architectures and impact of interface oxide charges R Narang, M Saxena, M Gupta 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS), 1-6, 2014 | 3 | 2014 |
| Surface potential based analytical model for hetero-dielectric pnin double-gate tunnel-FET Upasana, R Narang, M Saxena, M Gupta Physics of Semiconductor Devices: 17th International Workshop on the Physics …, 2014 | 1 | 2014 |
| Design and Investigation of High Performance Magnesium Silicide Based Face Tunnel Field Effect Transistor M Khurana, Upasana, M Saxena, M Gupta Silicon 15 (11), 4991-4999, 2023 | | 2023 |
| Simulation Study on Stability Aspect of Dual Metal Dual Dielectric Based TFET Architectures Against Temperature Variations Upasana, R Narang, M Saxena, M Gupta The Physics of Semiconductor Devices: Proceedings of IWPSD 2017, 649-655, 2019 | | 2019 |
