| At-speed scan test with low switching activity EK Moghaddam, J Rajski, M Kassab, SM Reddy 2010 28th VLSI Test Symposium (VTS), 177-182, 2010 | 118 | 2010 |
| Embedded deterministic test points C Acero, D Feltham, Y Liu, E Moghaddam, N Mukherjee, M Patyra, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017 | 50 | 2017 |
| Embedded deterministic test points for compact cell-aware tests C Acero, D Feltham, F Hapke, E Moghaddam, N Mukherjee, ... 2015 IEEE International Test Conference (ITC), 1-8, 2015 | 34 | 2015 |
| Logic BIST with capture-per-clock hybrid test points E Moghaddam, N Mukherjee, J Rajski, J Solecki, J Tyszer, J Zawada IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 30 | 2018 |
| Test point insertion in hybrid test compression/LBIST architectures E Moghaddam, N Mukherjee, J Rajski, J Tyszer, J Zawada 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 28 | 2016 |
| Isometric test data compression A Kumar, M Kassab, E Moghaddam, N Mukherjee, J Rajski, SM Reddy, ... IEEE transactions on computer-aided design of integrated circuits and …, 2015 | 25 | 2015 |
| Low power compression utilizing clock-gating J Rajski, EK Moghaddam, SM Reddy 2011 IEEE International Test Conference, 1-8, 2011 | 21 | 2011 |
| At-speed scan testing with controlled switching activity J Rajski, EK Moghaddam, N Mukherjee, MA Kassab, X Lin US Patent 8,499,209, 2013 | 19 | 2013 |
| Low capture power at-speed test in EDT environment moghaddam 2010 IEEE International Test Conference, 1-10, 2010 | 18 | 2010 |
| Hardware protection via logic locking test points M Chen, E Moghaddam, N Mukherjee, J Rajski, J Tyszer, J Zawada IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 17 | 2018 |
| Design for low test pattern counts H Konuk, E Moghaddam, N Mukherjee, J Rajski, D Solanki, J Tyszer, ... Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 15 | 2015 |
| Minimal area test points for deterministic patterns Y Liu, E Moghaddam, N Mukherjee, SM Reddy, J Rajski, J Tyszer 2016 IEEE International Test Conference (ITC), 1-7, 2016 | 14 | 2016 |
| Test time and area optimized brst scheme for automotive ics N Mukherjee, D Tille, M Sapati, Y Liu, J Mayer, S Milewski, E Moghaddam, ... 2019 IEEE International Test Conference (ITC), 1-10, 2019 | 13 | 2019 |
| On new test points for compact cell-aware tests C Acero, D Feltham, M Patyra, F Hapke, E Moghaddam, N Mukherjee, ... IEEE Design & Test 33 (6), 7-14, 2016 | 13 | 2016 |
| Low test data volume low power at-speed delay tests using clock-gating EK Moghaddam, J Rajski, SM Reddy, J Janicki 2011 Asian Test Symposium, 267-272, 2011 | 13 | 2011 |
| Time and area optimized testing of automotive ICs N Mukherjee, D Tille, M Sapati, Y Liu, J Mayer, S Milewski, E Moghaddam, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (1), 76-88, 2020 | 12 | 2020 |
| Power aware embedded test X Lin, E Moghaddam, N Mukherjee, B Nadeau-Dostie, J Rajski, J Tyszer 2011 Asian Test Symposium, 511-516, 2011 | 11 | 2011 |
| On test points enhancing hardware security E Moghaddam, N Mukherjee, J Rajski, J Tyszer, J Zawada 2016 IEEE 25th Asian Test Symposium (ATS), 61-66, 2016 | 10 | 2016 |
| Isometric test compression with low toggling activity A Kumar, M Kassab, E Moghaddam, N Mukherjee, J Rajski, SM Reddy, ... 2014 International Test Conference, 1-7, 2014 | 8 | 2014 |
| Low Power Scan-Based Testing J Rajski, EK Moghaddam US Patent App. 13/365,154, 2012 | 5 | 2012 |
