Dipankar Saha
Dipankar Saha
Dept. of Electronics & Telecommunication Engineering, IIEST Shibpur
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Atomistic modeling of the metallic-to-semiconducting phase boundaries in monolayer MoS2
D Saha, S Mahapatra
Applied Physics Letters 108 (http://dx.doi.org/10.1063/1.4954257), 253106-1 …, 2016
292016
Near-Direct Bandgap WSe2/ReS2 Type-II pn Heterojunction for Enhanced Ultrafast Photodetection and High-Performance Photovoltaics
A Varghese, D Saha, K Thakar, V Jindal, S Ghosh, NV Medhekar, ...
Nano letters 20 (3), 1707-1717, 2020
222020
Analytical insight into the lattice thermal conductivity and heat capacity of monolayer MoS2
D Saha, S Mahapatra
Physica E: Low-dimensional Systems and Nanostructures, 2016
202016
Photo-tunable transfer characteristics in MoTe2–MoS2 vertical heterostructure
AK Paul, M Kuiri, D Saha, B Chakraborty, S Mahapatra, AK Sood, A Das
npj 2D Materials and Applications 17 (doi:10.1038/s41699-017-0017-3), 2017
182017
Asymmetric Junctions in Metallic– Semiconducting–Metallic Heterophase MoS2
D Saha, S Mahapatra
IEEE TRANSACTIONS ON ELECTRON DEVICES 64 (5), 2457 - 2460, 2017
182017
Scalability assessment of Group-IV mono-chalcogenide based tunnel FET
M Brahma, A Kabiraj, D Saha, S Mahapatra
Scientific Reports, 2018
142018
Anisotropic transport in 1T′ monolayer MoS2 and its metal interfaces
D Saha, S Mahapatra
Physical Chemistry Chemical Physics 201719 (DOI: 10.1039/C7CP00816C), 10453 …, 2017
132017
A low power, high speed, IF range flash type ADC designed with the concept of TMCC and binary counter
S Mukherjee, D Saha, P Mostafa, D Saha, S Chatterjee, CK Sarkar
2012 Annual IEEE India Conference (INDICON), 092-097, 2012
132012
Theoretical insights on the electro-thermal transport properties of monolayer MoS2 with line defects
D Saha, S Mahapatra
JOURNAL OF APPLIED PHYSICS 119, 134304-1 to 134304-9, 2016
92016
A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications
S Mukherjee, D Saha, P Mostafa, S Chatterjee, CK Sarkar
2012 International Symposium on Electronic System Design (ISED), 28-32, 2012
62012
Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, modified with the concept of MVT Scheme
S Basak, D Saha, S Mukherjee, S Chatterjee, CK Sarkar
62012
Atomistic Modeling of van der Waals Heterostructures with Group‑6 and Group‑7 Monolayer Transition Metal Dichalcogenides for Near Infrared/Short-wave Infrared Photodetection
D Saha, A Varghese, S Lodha
ACS Appl. Nano Mater., 2019
52019
An Optimized Analog Layout for a Low Power 3-bit Flash Type ADC modified with the CMOS Inverter based Comparator Designs
D Basu, S Mukherjee, D Saha, S Chatterjee
42013
Effect of Line Defects on the Electrical Transport Properties of Monolayer MoS2 Sheet
A Sengupta, D Saha, TA Niehaus, S Mahapatra
IEEE Transactions on Nanotechnology 14 (1), 51-56, 2014
32014
A Continuous Electrical Conductivity Model for Monolayer Graphene From Near Intrinsic to Far Extrinsic Region
S Bhattacharya, D Saha, A Bid, S Mahapatra
IEEE TRANSACTIONS ON ELECTRON DEVICES (DOI: 10.1109/TED.2014.2358683) 61 …, 2014
32014
Impact of Stone-Wales and lattice vacancy defects on the electro-thermal transport of the free standing structure of metallic ZGNR
D Saha, A Sengupta, S Bhattacharya, S Mahapatra
Journal of Computational Electronics 13 (4), 862-871, 2014
32014
Row-Based Dual Vdd Assignment, for a Level Converter Free CSA Design and Its Near-Threshold Operation
D Saha, A Chatterjee, S Chatterjee, CK Sarkar
Advances in Electrical Engineering 2014 (Article ID 814975), 2014
22014
A low-voltage, Low-Power 4-bit BCD adder, designed using the Clock Gated Power Gating, and the DVT scheme
D Saha, S Basak, S Mukherjee, CK Sarkar
2013 IEEE International Conference on Signal Processing, Computing and …, 2013
22013
New Asymmetric Atomistic Model for the Analysis of Phase-Engineered MoS2-Gold Top Contact
R Chakravarty, D Saha, S Mahapatra
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
12018
Implementation of a new offset generator block for the low-voltage, low-power self biased threshold voltage extractor circuit
R Dasgupta, D Saha, J Samanta, S Chatterjee, CK Sarkar
Progress in VLSI Design and Test, 156-165, 2012
12012
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