| Reliability Aware Support Vector Machine Based High Level Surrogate Model For Analog Circuits S Khandelwal, L Garg, D Boolchandani Device and Materials Reliability, IEEE Transactions on 15 (3), 461-463, 2015 | 11 | 2015 |
| Variability aware yield optimal sizing of analog circuits using SVM-genetic approach D Boolchandani, L Garg, S Khandelwal, V Sahula Symbolic and Numerical Methods, Modeling and Applications to Circuit Design …, 2010 | 7 | 2010 |
| Macromodels for Static Virtual Ground Voltage Estimation in Power Gated Circuits L Garg, V Sahula IEEE Transactions on Circuits and Systems II: Express Briefs, 2015 | 6 | 2015 |
| Efficient CMOS subthreshold leakage analysis with improved stack based models in presence of parameter variations L Garg, V Sahula Electronics Letters 49 (10), 644-646, 2013 | 6 | 2013 |
| Variability aware SVM macromodel based design centering of analog circuits D Boolchandani, L Garg, S Khandelwal, V Sahula Analog Integrated Circuits and Signal Processing 73 (1), 77-87, 2012 | 5 | 2012 |
| Variability aware support vector machine based macromodels for statistical estimation of subthreshold leakage power L Garg, V Sahula Synthesis, Modeling, Analysis and Simulation Methods and Applications to …, 2012 | 5 | 2012 |
| Variability aware transistor stack based regression surrogate models for accurate and efficient statistical leakage estimation L Garg Microelectronics Journal 69, 1-19, 2017 | 4 | 2017 |
| Accurate and Efficient Estimation of Dynamic Virtual Ground Voltage in Power Gated Circuits L Garg, V Sahula VLSI Design and 2016 15th International Conference on Embedded Systems …, 2016 | 3 | 2016 |
| Variability and reliability aware surrogate model for sensing delay analysis of SRAM sense amplifier S Khandelwal, J Meena, L Garg, D Boolchandani VLSI Design and Test (VDAT), 2016 20th International Symposium on, 1-6, 2016 | 1 | 2016 |
| On Efficient And Accurate Surrogate Models Of Leakage In CMOS Gated Circuits... L Garg MNIT Jaipur, 2016 | 1 | 2016 |
| Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals N Navlakha, L Garg, D Boolchandani, V Sahula VLSI Design and Test, 312-321, 2013 | 1 | 2013 |
| Track-wise list of papers S Khandelwal, J Meena, L Garg, D Boolchandani, P Sharma, AK Gundu, ... | | |
D BoolchandaniProfessor of Electronics & Communication EngineeringVerified email at mnit.ac.in
D BoolchandaniProfessor of Electronics & Communication EngineeringVerified email at mnit.ac.in