Drive current boosting of n-type tunnel FET with strained SiGe layer at source N Patel, A Ramesha, S Mahapatra Microelectronics Journal 39 (12), 1671-1677, 2008 | 143 | 2008 |
Performance enhancement of the tunnel field effect transistor using a SiGe source NB Patel, A Ramesha, S Mahapatra 2007 International Workshop on Physics of Semiconductor Devices, 111-114, 2007 | 10 | 2007 |
Memory cell array latchup prevention RM Kapre, S Sharifzadeh, H Puchner, N Patel US Patent 9,842,629, 2017 | 4 | 2017 |
Stress voltage dependence HCI induced traps distribution in 60V LDNMOS SK Samanta, N Patel, KN ManjulaRani, K Jang 2009 IEEE International Integrated Reliability Workshop Final Report, 120-123, 2009 | 4 | 2009 |
Hot-carrier reliability study and simulation methodology development for 65nm technology KN ManjulaRani, RM Mooraka, N Patel, S Samanta, G Narasimhan, ... 2009 IEEE International Integrated Reliability Workshop Final Report, 124-127, 2009 | 4 | 2009 |
Correlation of soft error rates between mono-energetic and full spectrum beams on a 90nm SRAM technology NB Patel, H Puchner 2009 IEEE International Reliability Physics Symposium, 948-951, 2009 | 2 | 2009 |
0.4um high voltage CMOS smart power technology: 120V LD NMOS for integrated system on chip applications N Patel 16th International Workshop on Physics of Semiconductor Devices, 2012 | | 2012 |
Tunnel FET: Nano-Scale Switch For Low Standby Power Applications S Mahapatra, A Ramesha, N Patel | | 2008 |
Tunnel FET-A Novel Device with Sub-Threshold Swing less than 60 mV/decade for Future Low Stand-by Power Applications NB Patel, S Mahapatra | | 2007 |
A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications NB Patel, S Mahapatra Nano Scale Device Research Lab, 2007 | | 2007 |