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Prof. Manoj Saxena
Prof. Manoj Saxena
Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi, India
Verified email at ddu.du.ac.in - Homepage
Title
Cited by
Cited by
Year
A dielectric-modulated tunnel-FET-based biosensor for label-free detection: Analytical modeling study and sensitivity analysis
R Narang, KVS Reddy, M Saxena, RS Gupta, M Gupta
IEEE transactions on electron devices 59 (10), 2809-2817, 2012
1512012
Comparative analysis of dielectric-modulated FET and TFET-based biosensor
R Narang, M Saxena, M Gupta
IEEE Transactions on Nanotechnology 14 (3), 427-435, 2015
1182015
Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport …
M Saxena, S Haldar, M Gupta, RS Gupta
IEEE Transactions on Electron Devices 49 (11), 1928-1938, 2002
1172002
Dielectric modulated tunnel field-effect transistor—A biomolecule sensor
R Narang, M Saxena, RS Gupta, M Gupta
IEEE Electron Device Letters 33 (2), 266-268, 2011
1122011
Assessment of ambipolar behavior of a tunnel FET and influence of structural modifications
R Narang, M Saxena, RS Gupta, M Gupta
JSTS: Journal of Semiconductor Technology and Science 12 (4), 482-491, 2012
942012
Impact of Temperature Variations on the Device and Circuit Performance of Tunnel FET: A Simulation Study
R Narang, M Saxena, RS Gupta, M Gupta
IEEE Transactions on Nanotechnology 12 (6), 951-957, 2013
712013
Investigation of dielectric modulated (DM) double gate (DG) junctionless MOSFETs for application as a biosensors
R Narang, M Saxena, M Gupta
Superlattices and Microstructures 85, 557-572, 2015
622015
Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: Analog performance and linearity analysis
R Gautam, M Saxena, RS Gupta, M Gupta
Microelectronics Reliability 52 (6), 989-994, 2012
542012
Modeling and simulation of a nanoscale three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hot-electron effects
K Goel, M Saxena, M Gupta, RS Gupta
IEEE Transactions on Electron Devices 53 (7), 1623-1633, 2006
522006
Drain current model for a gate all around (GAA) p–n–p–n tunnel FET
R Narang, M Saxena, RS Gupta, M Gupta
Microelectronics Journal 44 (6), 479-488, 2013
482013
Analytical model of pH sensing characteristics of junctionless silicon on insulator ISFET
R Narang, M Saxena, M Gupta
IEEE Transactions on Electron Devices 64 (4), 1742-1750, 2017
452017
Gate all around MOSFET with vacuum gate dielectric for improved hot carrier reliability and RF performance
R Gautam, M Saxena, RS Gupta, M Gupta
IEEE transactions on electron devices 60 (6), 1820-1827, 2013
412013
Device and circuit level performance comparison of tunnel FET architectures and impact of heterogeneous gate dielectric
R Narang, M Saxena, RS Gupta, M Gupta
JSTS: Journal of Semiconductor Technology and Science 13 (3), 224-236, 2013
402013
Dual material double-layer gate stack SON MOSFET: A novel architecture for enhanced analog performance—Part I: Impact of gate metal workfunction engineering
P Kasturi, M Saxena, M Gupta, RS Gupta
IEEE transactions on electron devices 55 (1), 372-381, 2007
402007
Design considerations for novel device architecture: hetero-material double-gate (HEM-DG) MOSFET with sub-100 nm gate length
M Saxena, S Haldar, M Gupta, RS Gupta
Solid-State Electronics 48 (7), 1169-1174, 2004
402004
Modeling and TCAD assessment for gate material and gate dielectric engineered TFET architectures: circuit-level investigation for digital applications
R Narang, M Saxena, M Gupta
IEEE Transactions on Electron Devices 62 (10), 3348-3356, 2015
392015
GATE ALL AROUND MOSFET WITH CATALYTIC METAL GATE FOR GAS SENSING APPLICATIONS
R Gautam, M Saxena, RS Gupta, M Gupta
IEEE Transactions on Nanotechnology 12 (6), 939-944, 2013
392013
Numerical model of gate-all-around MOSFET with vacuum gate dielectric for biomolecule detection
R Gautam, M Saxena, RS Gupta, M Gupta
IEEE electron device letters 33 (12), 1756-1758, 2012
382012
TCAD assessment of gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET and its multilayered gate architecture—part I: hot-carrier-reliability evaluation
R Chaujar, R Kaur, M Saxena, M Gupta, RS Gupta
IEEE transactions on electron devices 55 (10), 2602-2613, 2008
372008
Two-dimensional analytical drain current model for double-gate MOSFET incorporating dielectric pocket
V Kumari, M Saxena, RS Gupta, M Gupta
IEEE transactions on electron devices 59 (10), 2567-2574, 2012
352012
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