| Design and implementation of single electron transistor N-BIT multiplier V Raut, PK Dakhole 2014 International Conference on Circuits, Power and Computing Technologies …, 2014 | 10 | 2014 |
| Design and implementation of four bit arithmetic and logic unit using hybrid single electron transistor and MOSFET at 120nm technology V Raut, PK Dakhole 2015 International Conference on Pervasive Computing (ICPC), 1-6, 2015 | 9 | 2015 |
| Design and implementation of quaternary summation circuit with single electron transistor and MOSFET V Raut, P Dakhole 2016 International Conference on Electrical, Electronics, and Optimization …, 2016 | 4 | 2016 |
| Design and Implementation of Hybrid Multiple Valued Logic Error Detector using Single Electron Transistor and CMOS at 120nm Technology VP Raut IOP Conference Series: Materials Science and Engineering 225 (1), 012160, 2017 | 2 | 2017 |
| Design and implementation of binary and quaternary low power selective circuit using single electron transistor V Raut, PK Dakhole 2015 International Conference on Control, Instrumentation, Communication and …, 2015 | 1 | 2015 |
| Review on Deign of 16-Bit Quaternary Adder using Various Encoding Techniques GM Kathalkar, V Raut International Journal of Computer Applications 975, 8887, 0 | | |
