| Low cost functional obfuscation of reusable IP cores used in CE hardware through robust locking A Sengupta, D Kachave, D Roy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 25 | 2018 |
| Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath … D Kachave, A Sengupta Microelectronics Reliability 60, 141-152, 2016 | 14 | 2016 |
| Low cost fault tolerance against kc-cycle and km-unit transient for loop based control data flow graphs during physically aware high level synthesis A Sengupta, D Kachave Microelectronics Reliability 74, 88-99, 2017 | 11 | 2017 |
| Spatial and temporal redundancy for transient fault-tolerant datapath A Sengupta, D Kachave IEEE Transactions on Aerospace and Electronic Systems 54 (3), 1168-1183, 2017 | 10 | 2017 |
| Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters] D Kachave, A Sengupta IEEE Consumer Electronics Magazine 7 (2), 111-114, 2018 | 5 | 2018 |
| Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis A Sengupta, D Kachave Future Generation Computer Systems 80, 29-46, 2018 | 5 | 2018 |
| Particle swarm optimisation driven low cost single event transient fault secured design during architectural synthesis A Sengupta, D Kachave The Journal of Engineering 2017 (6), 184-194, 2017 | 5 | 2017 |
| Generating multi-cycle and multiple transient fault resilient design during physically aware high level synthesis A Sengupta, D Kachave 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 75-80, 2016 | 5 | 2016 |
| Fault-Tolerant DSP Core Datapath Against Omnidirectional Spatial Impact of SET D Kachave, A Sengupta Canadian Journal of Electrical and Computer Engineering 42 (2), 102-107, 2019 | 3 | 2019 |
| Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation D Kachave, A Sengupta, S Neema, PS Harsha IET Computers & Digital Techniques 12 (6), 268-278, 2018 | 2 | 2018 |
| Applying digital forensic for hardware protection: Resolving false claim of IP core ownership D Kachave, A Sengupta IEEE VLSI Circuits and Systems Letter 4 (1), 10-13, 2018 | 2 | 2018 |
| Digital Processing Core Performance Degradation Due to Hardware Stress Attacks D Kachave, A Sengupta IEEE Potentials 38 (2), 39-45, 2019 | 1 | 2019 |
| Reliability and Threat analysis of NBTI Stress on DSP cores A Sengupta, D Kachave, S Neema, SH Panugothu 2017 IEEE International Symposium on Nanoelectronic and Information Systems …, 2017 | 1 | 2017 |
| Protecting ownership of reusable IP core generated during high level synthesis D Kachave, A Sengupta 2016 IEEE International Symposium on Nanoelectronic and Information Systems …, 2016 | 1 | 2016 |
| Transient fault reliability and security of IP cores D Kachave, A Sengupta Discipline of Computer Science and Engineering, IIT Indore, 2019 | | 2019 |
| Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores A Sengupta, D Kachave 2018 IEEE International Symposium on Smart Electronic Systems (iSES …, 2018 | | 2018 |
| IEEE VLSI Circuits and Systems Letter (VCAL)-TCVLSI R Kumar, S Sharma, D Kachave, A Sengupta, G Kumar, S Akashe, ... | | |
| Toward Secure and Trustworthy Cyberphysical Microfluidic Biochips....... J. Tang, M. Ibrahim, K. Chakrabarty, and R. Karri 589 A Sengupta, D Kachave, D Roy, Y Wang, M Zhang, X Yang, T Li | | |
Prof. Anirban Sengupta, Fellow IET, Fe...Full Professor, CSE, Indian Institute of Technology (IIT) IndoreVerified email at iiti.ac.in
