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Prabir Saha
Prabir Saha
Asst Professor of ECE, NIT meghalaya
Verified email at nitm.ac.in
Title
Cited by
Cited by
Year
High speed ASIC design of complex multiplier using vedic mathematics
P Saha, A Banerjee, P Bhattacharyya, A Dandapat
IEEE Technology Students' Symposium, 237-241, 2011
1332011
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics
P Saha, A Banerjee, A Dandapat, P Bhattacharyya
Microelectronics journal 42 (12), 1343-1352, 2011
442011
Improved matrix multiplier design for high‐speed digital signal processing applications
P Saha, A Banerjee, P Bhattacharyya, A Dandapat
IET circuits, devices & systems 8 (1), 27-37, 2014
262014
High speed low power complex multiplier design using parallel adders and subtractors
PK Saha, A Banerjee, A Dandapat
International Journal on Electronic and Electrical Engineering,(IJEEE) 7 (11 …, 2009
242009
Vedic divider: Novel architecture (ASIC) for high speed VLSI applications
P Saha, A Banerjee, P Bhattacharyya, A Dandapat
2011 International Symposium on Electronic System Design, 67-71, 2011
192011
Vedic mathematics based 32-bit multiplier design for high speed low power processors
P Saha, A Banerjee, A Dandapat, P Bhattacharyya
International journal on smart sensing and Intelligent Systems 4 (2), 2011
162011
Design of high speed vedic multiplier for decimal number system
P Saha, A Banerjee, A Dandapat, P Bhattacharyya
Progress in VLSI Design and Test, 79-88, 2012
152012
Vedic algorithm for cubic computation and VLSI implementation
D Kumar, P Saha, A Dandapat
Engineering science and technology, an international journal 20 (5), 1494-1499, 2017
122017
Hardware implementation of methodologies of fixed point division algorithms
D Kumar, P Saha, A Dandapat
International Journal on Smart Sensing and Intelligent Systems 10 (3), 1-16, 2017
122017
ASIC implementation of high speed processor for calculating discrete fourier transformation using circular convolution technique
P Saha, A Banerjee, A Dandapat, P Bhattacharyya
WSEAS Transactions on Circuits and Systems 10 (8), 278-288, 2011
112011
Vedic division methodology for high‐speed very large scale integration applications
P Saha, D Kumar, P Bhattacharyya, A Dandapat
The Journal of Engineering 2014 (2), 51-59, 2014
102014
4: 2 and 5: 2 Decimal Compressors
P Saha, P Samanta, D Kumar
2016 7th International Conference on Intelligent Systems, Modelling and …, 2016
72016
High speed multiplier using high accuracy floating point logarithmic number system
P Saha, A Banerjee, A Dandapat, P Bhattacharyya
Scientia Iranica 21 (3), 826-841, 2014
62014
Research Methodology in Agricultural Land Classification
PK Saha
Geographical Review of India, Calcutta 36 (2), 115-119, 1974
61974
New design approaches of reversible BCD encoder using Peres and Feynman gates
SD Thabah, P Saha
ICT Express 6 (1), 38-42, 2020
52020
Redesigned the architecture of extended-euclidean algorithm for modular multiplicative inverse and jacobi symbol
D Phiamphu, P Saha
2018 2nd International Conference on Trends in Electronics and Informatics …, 2018
52018
High speed low power floating point multiplier design based on CSD (canonical sign digit)
P Saha, A Banerjee, I Banerjee, A Dandapat
IEEE symposium on VLSI Design and Testing, 2010
52010
Experimental studies on multi-operand adders
SD Thabah, M Sonowal, P Saha
International Journal on Smart Sensing and Intelligent Systems 10 (2), 1-14, 2017
42017
Design of 64-bit squarer based on vedic mathematics
P Saha, D Kumar, P Bhattacharyya, A Dandapat
Journal of Circuits, Systems, and Computers 23 (07), 1450092, 2014
42014
Implementation Topology of Full Adder Cells
RU Ahmed, P Saha
Procedia Computer Science 165, 676-683, 2019
32019
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