| Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain DB Abdi, MJ Kumar IEEE Journal of the Electron Devices Society 2 (6), 187-190, 2014 | 304 | 2014 |
| In-Built N+ Pocket p-n-p-n Tunnel Field-Effect Transistor DB Abdi, MJ Kumar IEEE, 2014 | 154 | 2014 |
| Dielectric modulated overlapping gate-on-drain tunnel-FET as a label-free biosensor DB Abdi, MJ Kumar Superlattices and Microstructures 86, 198-202, 2015 | 94 | 2015 |
| Dopingless PNPN tunnel FET with improved performance: design and analysis MS Ram, DB Abdi Superlattices and Microstructures 82, 430-437, 2015 | 61 | 2015 |
| PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis DB Abdi, MJ Kumar Superlattices and Microstructures 86, 121-125, 2015 | 38 | 2015 |
| Single grain boundary tunnel field effect transistors on recrystallized polycrystalline silicon: Proposal and investigation MS Ram, DB Abdi IEEE Electron Device Letters 35 (10), 989-991, 2014 | 24 | 2014 |
| 2-D threshold voltage model for the double-gate pnpn TFET with localized charges DB Abdi, MJ Kumar IEEE Transactions on Electron Devices 63 (9), 3663-3668, 2016 | 20 | 2016 |
| Single grain boundary dopingless PNPN tunnel FET on recrystallized polysilicon: Proposal and theoretical analysis MS Ram, DB Abdi IEEE Journal of the Electron Devices Society 3 (3), 291-296, 2015 | 18 | 2015 |
| Suppressing ambipolar conduction using dual material gate in tunnel-FETs having heavily doped drain DB Abdi, MJ Kumar International Journal of Electronics and Communication Engineering 10 (5 …, 2016 | 9 | 2016 |
| Dopingless tunnel FET with a hetero-material gate: Design and analysis MS Ram, DB Abdi 2014 IEEE 2nd International Conference on Emerging Electronics (ICEE), 1-4, 2014 | 9 | 2014 |
| Performance investigation of single grain boundary junctionless field effect transistor MS Ram, DB Abdi IEEE Journal of the Electron Devices Society 4 (6), 480-484, 2016 | 7 | 2016 |
| Extended methodology to determine SRAM write margin in resistance-dominated technology node HH Liu, SM Salahuddin, D Abdi, R Chen, P Weckx, P Matagne, F Catthoor IEEE Transactions on Electron Devices 69 (6), 3113-3117, 2022 | 5 | 2022 |
| Stt-mram stochastic and defects-aware dtco for last level cache at advanced process nodes F García-Redondo, S Rao, M Gupta, M Perumkunnil, Y Xiang, D Abdi, ... ESSDERC 2023-IEEE 53rd European Solid-State Device Research Conference …, 2023 | 2 | 2023 |
| Drain induced barrier widening and reverse short channel effects in tunneling FETs: investigation and analysis MK Ram, N Tiwari, DB Abdi, S Saurabh Ieee Access 9, 150366-150372, 2021 | 2 | 2021 |
| Ultimate MRAM Scaling: Design Exploration of High-Density, High-Performance and Energy-Efficient VGSOT for Last Level Cache M Gupta, Y Xiangt, F García-Redondo, K Cai, D Abdi, HH Liu, S Rao, ... 2023 International Electron Devices Meeting (IEDM), 1-4, 2023 | 1 | 2023 |
| 3D SRAM Macro Design in 3D Nanofabric Process Technology DB Abdi, SM Salahuddin, J Boemmels, E Giacomin, P Weckx, J Ryckaert, ... IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | 1 | 2023 |
| Effect of drain induced barrier enhancement on subthreshold swing and off-state current of short channel mosfets: A tcad study MK Ram, N Tiwari, DB Abdi, S Saurabh Ieee Access 9, 141321-141328, 2021 | 1 | 2021 |
| 3D Integrated Circuit F Catthoor, DB Abdi US Patent App. 18/482,263, 2024 | | 2024 |
| 2023 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 70 E Abbasian, A Abdelhafiz, BA Abdelmagid, DB Abdi, AA Abidi, ... IEEE Transactions on Circuits and Systems I: Regular Papers 70 (12), 2023 | | 2023 |
| Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs) S Mishra, V Sankatali, B Vermeersch, M Brunion, M Lofrano, D Abdi, ... 2023 IEEE International Reliability Physics Symposium (IRPS), 1-7, 2023 | | 2023 |
Mamidala Jagadesh Kumar.Indian Institute of Technology Delhi; Chairman, UGCVerified email at ee.iitd.ac.in
