Kunle Olukotun
Kunle Olukotun
Cadence Design Systems Professor of Computer Science, Stanford University
Verified email at stanford.edu - Homepage
TitleCited byYear
Map-reduce for machine learning on multicore
CT Chu, SK Kim, YA Lin, YY Yu, G Bradski, K Olukotun, AY Ng
Advances in neural information processing systems, 281-288, 2007
Niagara: A 32-way multithreaded sparc processor
P Kongetira, K Aingaran, K Olukotun
IEEE micro 25 (2), 21-29, 2005
The case for a single-chip multiprocessor
K Olukotun, BA Nayfeh, L Hammond, K Wilson, K Chang
ACM Sigplan Notices 31 (9), 2-11, 1996
STAMP: Stanford transactional applications for multi-processing
CC Minh, JW Chung, C Kozyrakis, K Olukotun
2008 IEEE International Symposium on Workload Characterization, 35-46, 2008
Transactional memory coherence and consistency
L Hammond, V Wong, M Chen, BD Carlstrom, JD Davis, B Hertzberg, ...
ACM SIGARCH Computer Architecture News 32 (2), 102, 2004
A single-chip multiprocessor
BA Nayfeh, K Olukotun
Computer 30 (9), 79-85, 1997
The stanford hydra cmp
L Hammond, BA Hubbert, M Siu, MK Prabhu, M Chen, K Olukolun
IEEE micro 20 (2), 71-84, 2000
Data speculation support for a chip multiprocessor
L Hammond, M Willey, K Olukotun
ACM SIGOPS Operating Systems Review 32 (5), 58-69, 1998
An effective hybrid transactional memory system with strong isolation guarantees
CC Minh, M Trautmann, JW Chung, A McDonald, N Bronson, J Casper, ...
ACM SIGARCH Computer Architecture News 35 (2), 69-80, 2007
The future of microprocessors
K Olukotun, L Hammond
Queue 3 (7), 26-29, 2005
Accelerating CUDA graph algorithms at maximum warp
S Hong, SK Kim, T Oguntebi, K Olukotun
Acm Sigplan Notices 46 (8), 267-276, 2011
REMARC: Reconfigurable multimedia array coprocessor
T Miyamori, K Olukotun
IEICE Transactions on information and systems 82 (2), 389-397, 1999
Efficient parallel graph exploration on multi-core CPU and GPU
S Hong, T Oguntebi, K Olukotun
2011 International Conference on Parallel Architectures and Compilation …, 2011
Architectural semantics for practical transactional memory
A McDonald, JW Chung, BD Carlstrom, CC Minh, H Chafi, C Kozyrakis, ...
ACM SIGARCH Computer Architecture News 34 (2), 53-65, 2006
Green-Marl: a DSL for easy and efficient graph analysis
S Hong, H Chafi, E Sedlar, K Olukotun
ACM SIGARCH Computer Architecture News 40 (1), 349-362, 2012
Lightweight modular staging: a pragmatic approach to runtime code generation and compiled DSLs
T Rompf, M Odersky
Acm Sigplan Notices 46 (2), 127-136, 2010
Liszt: a domain specific language for building portable mesh-based PDE solvers
Z DeVito, N Joubert, F Palacios, S Oakley, M Medina, M Barrientos, ...
Proceedings of 2011 International Conference for High Performance Computing …, 2011
In search of speculative thread-level parallelism
JT Oplinger, DL Heine, MS Lam
1999 International Conference on Parallel Architectures and Compilation …, 1999
A quantitative analysis of reconfigurable coprocessors for multimedia applications
T Miyamori, U Olukotun
Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No …, 1998
A heterogeneous parallel framework for domain-specific languages
KJ Brown, AK Sujeeth, HJ Lee, T Rompf, H Chafi, M Odersky, K Olukotun
2011 International Conference on Parallel Architectures and Compilation …, 2011
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