Pankaj Kumar Pal
Pankaj Kumar Pal
Assistant Professor, Department of Electronics Engineering, NIT Uttarakhand
Verified email at gov.in - Homepage
TitleCited byYear
High-Performance and Robust SRAM Cell Based on Asymmetric Dual-k Spacer FinFETs
PK Pal, BK Kaushik, S Dasgupta
IEEE Transactions on Electron Devices 60 (10), 3371 - 3377, 2013
502013
Investigation of Symmetric Dual-(k) Spacer Trigate FinFETs From Delay Perspective
PK Pal, BK Kaushik, S Dasgupta
IEEE transactions on electron devices 61 (11), 2014
342014
Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis
PK Pal, BK Kaushik, S Dasgupta
IEEE Transactions on Electron Devices 62 (4), 1105-1112, 2015
222015
New low-power techniques: Leakage Feedback with Stack & Sleep Stack with Keeper
PK Pal, RS Rathore, AK Rana, G Saini
Computer and Communication Technology (ICCCT), 2010 International Conference …, 2010
192010
Design Metrics Improvement for SRAMs Using Symmetric Dual-k Spacer (SymD-k) FinFETs
PK Pal, BK Kaushik, S Dasgupta
IEEE Transactions on Electron Devices 61 (4), 1123-1130, 2014
152014
Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers
PK Pal, BK Kaushik, S Dasgupta
VLSI Design and Test, 267-273, 2013
52013
Leakage behavior of underlap FinFET structure: A simulation study
G Saini, AK Rana, PK Pal, S Jadav
Computer and Communication Technology (ICCCT), 2010 International Conference …, 2010
52010
Performance analysis of dual-k spacer at source side for underlap FinFETs
PK Pal, P Singh, BK Kaushik, B Anand, S Dasgupta
India Conference (INDICON), 2012 Annual IEEE, 915-919, 2012
42012
Spacer Engineered FinFET Architectures: High-performance Digital Circuit Applications
BK Kaushik, S Dasgupta, PK Pal
CRC Press, 2017
32017
Low-power and robust 6T SRAM cell using symmetric dual-k spacer FinFETs
PK Pal, BK Kaushik, S Dasgupta
Microelectronics Proceedings-MIEL 2014, 2014 29th International Conference …, 2014
32014
A detailed capacitive analysis of symmetric and asymmetric dual-k FinFETs for improved circuit delay metrics
PK Pal, BK Kaushik, S Dasgupta
Emerging Devices and Smart Systems (ICEDSS), Conference on, 13-18, 2016
22016
Performance Analysis of CNTs as an Application for Future VLSI Interconnects
S Sharma, R Chandel, PK Pal, RS Rathore
Microelectronics and Solid State Electronics 1 (3), 69-73, 2012
22012
Performance Enhancement of STT MRAM Using Asymmetric-Sidewall-Spacer NMOS
S Verma, PK Pal, S Mahawar, BK Kaushik
IEEE Transactions on Electron Devices 63 (7), 2771-2776, 2016
12016
A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives
PK Pal, BK Kaushik, B Anand, S Dasgupta
Quality Electronic Design (ISQED), 2015 16th International Symposium on, 594-598, 2015
12015
High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications
D Nehra, PK Pal, BK Kaushik, S Dasgupta
VLSI Design and Test, 18th International Symposium on, 1-6, 2014
12014
Enhanced device performance using lightly doped channel junctionless accumulation-mode FinFET
PK Pal, D Nehra, BK Kaushik, S Dasgupta
Electrical Engineering/Electronics, Computer, Telecommunications and …, 2015
2015
Statistical variability and sensitivity analysis of dual-k spacer FinFET device-circuit co-design
PK Pal, S Verma, BK Kaushik, S Dasgupta
Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International …, 2015
2015
Highly reliable STT MRAM using fully depleted body and buried 4H-SiC NMOS
S Mahawar, S Verma, PK Pal, BK Kaushik
Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International …, 2015
2015
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