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Valerio Tenace
Valerio Tenace
Verified email at utah.edu
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Year
Logic synthesis meets machine learning: Trading exactness for generalization
S Rai, WL Neto, Y Miyasaka, X Zhang, M Yu, Q Yi, M Fujita, GB Manske, ...
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021
292021
A clinically applicable approach to the classification of B-cell non-Hodgkin lymphomas with flow cytometry and machine learning
V Gaidano, V Tenace, N Santoro, S Varvello, A Cignetti, G Prato, G Saglio, ...
Cancers 12 (6), 1684, 2020
252020
The synergism between DHODH inhibitors and dipyridamole leads to metabolic lethality in acute myeloid leukemia
V Gaidano, M Houshmand, N Vitale, G Carrà, A Morotti, V Tenace, ...
Cancers 13 (5), 1003, 2021
242021
SAID: A supergate-aided logic synthesis flow for memristive crossbars
V Tenace, RG Rizzo, D Bhattacharjee, A Chattopadhyay, A Calimera
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 372-377, 2019
182019
Pass-XNOR logic: A new logic style for PN junction based graphene circuits
V Tenace, A Calimera, E Macii, M Poncino
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
172014
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits
V Tenace, A Calimera, E Macii, M Poncino
Proceedings of the 52Nd Annual Design Automation Conference, 1-6, 2015
132015
Layer-wise compressive training for convolutional neural networks
M Grimaldi, V Tenace, A Calimera
Future Internet 11 (1), 7, 2018
112018
Energy-efficient convolutional neural networks via recurrent data reuse
L Mocerino, V Tenace, A Calimera
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 848-853, 2019
82019
Ultra-low power circuits using graphene p–n junctions and adiabatic computing
S Miryala, V Tenace, A Calimera, E Macii, M Poncino
Microprocessors and Microsystems 39 (8), 962-972, 2015
82015
Quasi-adiabatic logic arrays for silicon and beyond-silicon energy-efficient ICs
V Tenace, A Calimera, E Macii, M Poncino
IEEE Transactions on Circuits and Systems II: Express Briefs 63 (12), 1111-1115, 2016
72016
Exploiting the expressive power of graphene reconfigurable gates via post-synthesis optimization
S Miryala, V Tenace, A Calimera, E Macii, M Poncino, L Amarú, ...
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 39-44, 2015
72015
Logic synthesis of pass-gate logic circuits with emerging ambipolar technologies
V Tenace, A Calimera, E Macii, M Poncino
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
62018
Activation-kernel extraction through machine learning
V Tenace, A Calimera
2017 New Generation of CAS (NGCAS), 5-8, 2017
62017
A clinically applicable approach to the classification of B-cell non-Hodgkin lymphomas with flow cytometry and machine learning. Cancers. 2020; 12 (6): 1684
V Gaidano, V Tenace, N Santoro, S Varvello, A Cignetti, G Prato, G Saglio, ...
52020
Multiplication by inference using classification trees: A case-study analysis
RG Rizzo, V Tenace, A Calimera
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
52018
Inferential logic: A machine learning inspired paradigm for combinational circuits
V Tenace, A Calimera
2018 IFIP/IEEE International Conference on Very Large Scale Integration …, 2018
42018
Graphene-PLA (GPLA) a Compact and Ultra-Low Power Logic Array Architecture
V Tenace, A Calimera, E Macii, M Poncino
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 145-150, 2016
42016
Row-based body-bias assignment for dynamic thermal clock-skew compensation
V Tenace, S Miryala, A Calimera, A Macii, E Macii, M Poncino
Microelectronics Journal 45 (5), 530-538, 2014
42014
NBTI effects on tree-like clock distribution networks
W Liu, S Miryala, V Tenace, A Calimera, E Macii, M Poncino
Proceedings of the great lakes symposium on VLSI, 279-282, 2012
42012
Quasi-exact logic functions through classification trees
V Tenace, A Calimera
Integration 63, 248-255, 2018
32018
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Articles 1–20